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Ozgur Sinanoglu

32 papers hereh-index 7227 citations84 works total

Matching runs newest-first, so older work may not be attached to this profile yet.

author position
  • middle author25
  • last author7

Across the 32 of 32 papers where every author was matched, so the position is known.

fields
  • cs.CR18
  • cs.AR6
  • cs.LG5
  • cs.CL1
  • cs.CY1
  • eess.SY1
same name
  • Ozgur Sinanoglu — 1 paper

Either other researchers who publish under this name, or the same person where the external sources have not merged their records.

identity via Semantic Scholar / OpenAlex

activity
20242026
most citedTroLLoc: Logic Locking and Layout Hardening for IC Security Closure against Hardware Trojans

2 citations · 6 across the 30 of their papers we have counts for

collaborators
Showing 2025 · cs.ARShow all

2 papers · 2 filters

cs.AR2025★ 1 cited

Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form

Prithwish Basu Roy, Akashdeep Saha, Manaar Alam +4

Automated Verilog code synthesis poses significant challenges and typically demands expert oversight. Traditional high-level synthesis (HLS) methods often fail to scale for real-wo…

cs.AR2025★ 1 cited

VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contamination

Zeng Wang, Minghao Shao, Jitendra Bhandari +5

Large Language Models (LLMs) have revolutionized code generation, achieving exceptional results on various established benchmarking frameworks. However, concerns about data contami…

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