10 papers
CoEvoP&R: Co-Evolving Placement Objectives with Routing Feedback via Large Language Models
Ruogu Chen, Weihua Xiao, Ramesh Karri +1
Analytical placers rely on differentiable objective functions to guide placement, typically combining intermediate surrogate metrics such as half-perimeter wirelength (HPWL) and ce…
VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilog
Prithwish Basu Roy, Zeng Wang, Anatolii Chuvashlov +4
Large Language Models (LLMs) have shown significant improvement in RTL code generation. Despite the advances, the generated code is often riddled with common vulnerabilities and we…
GUIDE: GenAI Units In Digital Design Education
Weihua Xiao, Jason Blocklove, Matthew DeLorenzo +6
GenAI Units In Digital Design Education (GUIDE) is an open courseware repository with runnable Google Colab labs and other materials. We describe the repository's architecture and…
LLM4PQC - Accurate and Efficient Synthesis of PQC Cores by Feedback-Driven LLMs
Buddhi Perera, Zeng Wang, Weihua Xiao +4
The design of post-quantum cryptography (PQC) hardware is a complex and hierarchical process with many challenges. A primary bottleneck is the conversion of PQC reference codes fro…
TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertion
Saideep Sreekumar, Zeng Wang, Akashdeep Saha +6
Hardware Trojans (HTs) remain a critical threat because learning-based detectors often overfit to narrow trigger/payload patterns and small, stylized benchmarks. We introduce Troja…
TrojanLoC: LLM-based Framework for RTL Trojan Localization
Weihua Xiao, Zeng Wang, Minghao Shao +6
Hardware Trojans (HT s) are a persistent threat to integrated circuits, especially when inserted at the register-transfer level (RTL). Existing methods typically first convert the…
VeriDispatcher: Multi-Model Dispatching through Pre-Inference Difficulty Prediction for RTL Generation Optimization
Zeng Wang, Weihua Xiao, Minghao Shao +4
Large Language Models (LLMs) show strong performance in RTL generation, but different models excel on different tasks because of architecture and training differences. Prior work m…
Hybrid-NL2SVA: Integrating RAG and Finetuning for LLM-based NL2SVA
Weihua Xiao, Derek Ekberg, Siddharth Garg +1
SystemVerilog Assertions (SVAs) are critical for verifying the correctness of hardware designs, but manually writing them from natural language property descriptions, i.e., NL2SVA,…
VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification
Patrick Yubeaton, Andre Nakkab, Weihua Xiao +4
This paper introduces VeriThoughts, a novel dataset designed for reasoning-based Verilog code generation. We establish a new benchmark framework grounded in formal verification met…
PrefixLLM: LLM-aided Prefix Circuit Design
Weihua Xiao, Venkata Sai Charan Putrevu, Raghu Vamshi Hemadri +2
Prefix circuits are fundamental components in digital adders, widely used in digital systems due to their efficiency in calculating carry signals. Synthesizing prefix circuits with…