12 papers
CMD: An Integrated CGRA Framework with Cluster-Based Distributed Memory Design
Shangkun Li, Cheng Tan, Zeyu Li +6
Coarse-Grained Reconfigurable Arrays (CGRAs) are a promising solution for achieving high energy efficiency and reconfigurability across various application domains, but their perfo…
APEX-RBD: Mixed-Precision Exploration Framework for Hardware-Efficient Robot Dynamics Accelerator Design
Xingyu Liu, Hanwei Fan, Chaofang Ma +4
Rigid Body Dynamics (RBD) forms the computational core of real-time robotic control, but its immense computational complexity creates a performance bottleneck that necessitates ded…
Not All Attention Heads Contribute to Critical Visual Token Selection: Head-Aware Pruning Matters More
Chaofang Ma, Lin Jiang, Carol Jingyi Li +4
Vision-Language Models (VLMs) have exhibited impressive performance across diverse visual scenarios. However, this success comes at the cost of explosive growth in visual tokens, w…
PICopilot: An LLM-based Agentic Framework for Assisting Photonic Integrated Circuit Design via Script Generation
Xiaohan Jiang, Zeyu Li, Wei Zhang +1
The rapid development of photonic integrated circuits (PICs) is shifting the design flow from traditional graphical user interface (GUI)-based methods to script-based methods for h…
FPGN: Redefining Ultra-Fast Programmable Gate-based Neural Acceleration with Differentiable LUTs
Jiawei Liang, Haotong Qin, Linfeng Du +7
Achieving nanosecond-scale inference latency for deep neural networks (DNNs) has become a primary architectural concern for latency-critical applications. While Field-Programmable…
HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing
Ya Wang, Hanwei Fan, Zhenguo Liu +4
Modern processor verification struggles to reach deep architectural states due to the inefficiencies of traditional mutation-based fuzzing. We propose HiFuzz, a novel hierarchical…
NEURA: A Unified and Retargetable Compilation Framework for Coarse-Grained Reconfigurable Architectures
Shangkun Li, Jinming Ge, Diyuan Tao +6
Coarse-Grained Reconfigurable Architectures (CGRAs) are a promising and versatile accelerator platform, offering a balance between the performance and efficiency of specialized acc…
VersaQ-3D: Architecture Support for Visual Geometry Grounded Transformers via Versatile Quantization
Yipu Zhang, Jintao Cheng, Xingyu Liu +8
3D reconstruction and view synthesis are fundamental to AR/VR, robotics, and digital twins. The Visual Geometry Grounded Transformer (VGGT) enables strong feed-forward 3D reconstru…
FLEX: Leveraging FPGA-CPU Synergy for Mixed-Cell-Height Legalization Acceleration
Xingyu Liu, Jiawei Liang, Linfeng Du +5
In this work, we present FLEX, an FPGA-CPU accelerator for mixed-cell-height legalization tasks. We address challenges from the following perspectives. First, we optimize the task…
DRACO: Co-design for DSP-Efficient Rigid Body Dynamics Accelerator
Xingyu Liu, Jiawei Liang, Yipu Zhang +5
We propose a hardware-efficient RBD accelerator based on FPGA, introducing three key innovations. First, we propose a precision-aware quantization framework that reduces DSP demand…
HERO: Hardware-Efficient RL-based Optimization Framework for NeRF Quantization
Yipu Zhang, Chaofang Ma, Jinming Ge +3
Neural Radiance Field (NeRF) has emerged as a promising 3D reconstruction method, delivering high-quality results for AR/VR applications. While quantization methods and hardware ac…
SpNeRF: Memory Efficient Sparse Volumetric Neural Rendering Accelerator for Edge Devices
Yipu Zhang, Jiawei Liang, Jian Peng +2
Neural rendering has gained prominence for its high-quality output, which is crucial for AR/VR applications. However, its large voxel grid data size and irregular access patterns c…