6 papers · 1 filter
VIKIN: A Reconfigurable Accelerator for KANs and MLPs with Two-Stage Sparsity Support
Wenhui Ou, Zhuoyu Wu, Yipu Zhang +2
Recently, multi-layer perceptrons (MLPs) widely used in modern AI applications suffer from limited real-time performance due to intensive memory access overhead. Kolmogorov--Arnold…
FLICKER: A Fine-Grained Contribution-Aware Accelerator for Real-Time 3D Gaussian Splatting
Wenhui Ou, Zhuoyu Wu, Yipu Zhang +3
Recently, 3D Gaussian Splatting (3DGS) has emerged as a mainstream rendering technique due to its photorealistic quality and low latency. However, processing massive numbers of non…
FLEX: Leveraging FPGA-CPU Synergy for Mixed-Cell-Height Legalization Acceleration
Xingyu Liu, Jiawei Liang, Linfeng Du +5
In this work, we present FLEX, an FPGA-CPU accelerator for mixed-cell-height legalization tasks. We address challenges from the following perspectives. First, we optimize the task…
DRACO: Co-design for DSP-Efficient Rigid Body Dynamics Accelerator
Xingyu Liu, Jiawei Liang, Yipu Zhang +5
We propose a hardware-efficient RBD accelerator based on FPGA, introducing three key innovations. First, we propose a precision-aware quantization framework that reduces DSP demand…
HERO: Hardware-Efficient RL-based Optimization Framework for NeRF Quantization
Yipu Zhang, Chaofang Ma, Jinming Ge +3
Neural Radiance Field (NeRF) has emerged as a promising 3D reconstruction method, delivering high-quality results for AR/VR applications. While quantization methods and hardware ac…
SpNeRF: Memory Efficient Sparse Volumetric Neural Rendering Accelerator for Edge Devices
Yipu Zhang, Jiawei Liang, Jian Peng +2
Neural rendering has gained prominence for its high-quality output, which is crucial for AR/VR applications. However, its large voxel grid data size and irregular access patterns c…