6 papers · 1 filter
CMD: An Integrated CGRA Framework with Cluster-Based Distributed Memory Design
Shangkun Li, Cheng Tan, Zeyu Li +6
Coarse-Grained Reconfigurable Arrays (CGRAs) are a promising solution for achieving high energy efficiency and reconfigurability across various application domains, but their perfo…
APEX-RBD: Mixed-Precision Exploration Framework for Hardware-Efficient Robot Dynamics Accelerator Design
Xingyu Liu, Hanwei Fan, Chaofang Ma +4
Rigid Body Dynamics (RBD) forms the computational core of real-time robotic control, but its immense computational complexity creates a performance bottleneck that necessitates ded…
FPGN: Redefining Ultra-Fast Programmable Gate-based Neural Acceleration with Differentiable LUTs
Jiawei Liang, Haotong Qin, Linfeng Du +7
Achieving nanosecond-scale inference latency for deep neural networks (DNNs) has become a primary architectural concern for latency-critical applications. While Field-Programmable…
FLEX: Leveraging FPGA-CPU Synergy for Mixed-Cell-Height Legalization Acceleration
Xingyu Liu, Jiawei Liang, Linfeng Du +5
In this work, we present FLEX, an FPGA-CPU accelerator for mixed-cell-height legalization tasks. We address challenges from the following perspectives. First, we optimize the task…
DRACO: Co-design for DSP-Efficient Rigid Body Dynamics Accelerator
Xingyu Liu, Jiawei Liang, Yipu Zhang +5
We propose a hardware-efficient RBD accelerator based on FPGA, introducing three key innovations. First, we propose a precision-aware quantization framework that reduces DSP demand…
SpNeRF: Memory Efficient Sparse Volumetric Neural Rendering Accelerator for Edge Devices
Yipu Zhang, Jiawei Liang, Jian Peng +2
Neural rendering has gained prominence for its high-quality output, which is crucial for AR/VR applications. However, its large voxel grid data size and irregular access patterns c…