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cs.LG2025
DAPO: Design Structure-Aware Pass Ordering in High-Level Synthesis with Graph Contrastive and Reinforcement Learning
Jinming Ge, Linfeng Du, Likith Anaparty +8
High-Level Synthesis (HLS) tools are widely adopted in FPGA-based domain-specific accelerator design. However, existing tools rely on fixed optimization strategies inherited from s…
cs.AR2025
FLEX: Leveraging FPGA-CPU Synergy for Mixed-Cell-Height Legalization Acceleration
Xingyu Liu, Jiawei Liang, Linfeng Du +5
In this work, we present FLEX, an FPGA-CPU accelerator for mixed-cell-height legalization tasks. We address challenges from the following perspectives. First, we optimize the task…
cs.AR2025
DRACO: Co-design for DSP-Efficient Rigid Body Dynamics Accelerator
Xingyu Liu, Jiawei Liang, Yipu Zhang +5
We propose a hardware-efficient RBD accelerator based on FPGA, introducing three key innovations. First, we propose a precision-aware quantization framework that reduces DSP demand…