5 papers
Structured Testbench Generation for LLM-Driven HDL Design and Verification-Oriented Data Curation
En-Ming Huang, Yu-Hung Kao, Ren-Hao Deng +10
Automated testbench generation has become a critical bottleneck in large language model (LLM)-driven Register Transfer Level (RTL) workflows, where large numbers of candidate desig…
Exploring LLM-based Verilog Code Generation with Data-Efficient Fine-Tuning and Testbench Automation
Mu-Chi Chen, Po-Hsuan Huang, Yu-Hung Kao +6
Recent advances in large language models have improved code generation, but their use in hardware description languages is still limited. Moreover, training data and testbenches fo…
SiliconMind-V1: Multi-Agent Distillation and Debug-Reasoning Workflows for Verilog Code Generation
Mu-Chi Chen, Yu-Hung Kao, Po-Hsuan Huang +10
Large language models (LLMs) have recently emerged as a promising approach for automating Verilog code generation; however, existing methods primarily emphasize syntactic correctne…
Efficiently Editing Mixture-of-Experts Models with Compressed Experts
Yifei He, Yang Liu, Chen Liang +1
Mixture-of-Experts (MoE) models have become a key approach for scaling large language models efficiently by activating only a subset of experts during training and inference. Typic…
Phi-4-Mini Technical Report: Compact yet Powerful Multimodal Language Models via Mixture-of-LoRAs
Microsoft, :, Abdelrahman Abouelenin +73
We introduce Phi-4-Mini and Phi-4-Multimodal, compact yet highly capable language and multimodal models. Phi-4-Mini is a 3.8-billion-parameter language model trained on high-qualit…