3 papers
cs.AI2026
Structured Testbench Generation for LLM-Driven HDL Design and Verification-Oriented Data Curation
En-Ming Huang, Yu-Hung Kao, Ren-Hao Deng +10
Automated testbench generation has become a critical bottleneck in large language model (LLM)-driven Register Transfer Level (RTL) workflows, where large numbers of candidate desig…
cs.AR2026
SiliconMind-V1: Multi-Agent Distillation and Debug-Reasoning Workflows for Verilog Code Generation
Mu-Chi Chen, Yu-Hung Kao, Po-Hsuan Huang +10
Large language models (LLMs) have recently emerged as a promising approach for automating Verilog code generation; however, existing methods primarily emphasize syntactic correctne…
cs.AI2026
EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimization
Wei-Po Hsin, Ren-Hao Deng, Yao-Ting Hsieh +2
Verilog's design cycle is inherently labor-intensive and necessitates extensive domain expertise. Although Large Language Models (LLMs) offer a promising pathway toward automation,…