activity
20232025
collaborators

7 papers

cs.CC2025

Bounded Dynamic Level Maintenance for Efficient Logic Optimization

Junfeng Liu, Qinghua Zhao, Liwei Ni +5

Logic optimization constitutes a critical phase within the Electronic Design Automation (EDA) flow, essential for achieving desired circuit power, performance, and area (PPA) targe…

cs.AR2025

BoolSkeleton: Boolean Network Skeletonization via Homogeneous Pattern Reduction

Liwei Ni, Jiaxi Zhang, Shenggen Zheng +5

Boolean equivalence allows Boolean networks with identical functionality to exhibit diverse graph structures. This gives more room for exploration in logic optimization, while also…

cs.AI2024

OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine Learning Tasks in Logic Synthesis

Liwei Ni, Rui Wang, Miao Liu +10

This paper introduces OpenLS-DGF, an adaptive logic synthesis dataset generation framework, to enhance machine learning~(ML) applications within the logic synthesis process. Previo…

cs.LG2024

Boolean-aware Boolean Circuit Classification: A Comprehensive Study on Graph Neural Network

Liwei Ni, Xinquan Li, Biwei Xie +1

Boolean circuit is a computational graph that consists of the dynamic directed graph structure and static functionality. The commonly used logic optimization and Boolean matching-b…

cs.DC2024

Parallel AIG Refactoring via Conflict Breaking

Ye Cai, Zonglin Yang, Liwei Ni +3

Algorithm parallelization to leverage multi-core platforms for improving the efficiency of Electronic Design Automation~(EDA) tools plays a significant role in enhancing the scalab…

cs.DC2024

Enhancing ASIC Technology Mapping via Parallel Supergate Computing

Ye Cai, Zonglin Yang, Liwei Ni +2

With the development of large-scale integrated circuits, electronic design automation~(EDA) tools are increasingly emphasizing efficiency, with parallel algorithms becoming a trend…

cs.AI2023

Adaptive Reconvergence-driven AIG Rewriting via Strategy Learning

Liwei Ni, Zonglin Yang, Jiaxi Zhang +4

Rewriting is a common procedure in logic synthesis aimed at improving the performance, power, and area (PPA) of circuits. The traditional reconvergence-driven And-Inverter Graph (A…