8 citations · 13 across the 15 of their papers we have counts for
16 papers
TomasuLLM: Out-of-Order Speculative Execution for LLM Agents
Jiangnan Yu, Ceyu Xu, Mengming Li +6
Long-running tools can dominate coding-agent latency: compilers, test suites, and repository commands take seconds to minutes while the agent idles. This observation stall presents…
Memory Compression for High-Fanout Agent Sandboxes
Mengming Li, Ceyu XU, Qijun Zhang +4
High-fanout agent workloads create a growing memory bottleneck because a single task may spawn many concurrent sandbox sessions. Yet these sandboxes are far from independent: they…
G-Power: Architecture-level GPU Power Modeling with Aggregated Knowledge Foundations from Known GPUs
Qijun Zhang, Yao Lu, Shang Liu +4
Graphics Processing Units (GPUs) have been serving as critical computation resources for large-scale parallel computations. With increasing chip complexity, power efficiency has be…
LEAP: A Self-Supervised Per-Cycle Toggle Propagation Model Supports Fast, Transferable, and Early Analysis of Layout Power
Wenkai Li, Yuchao Wu, Ziyan Guo +4
Accurate power analysis is critical in VLSI design, as it directly impacts power optimization strategies. However, traditional approaches are often hindered by the substantial runt…
ComPart: Community-Guided Post-Coarsening for High-Quality Hypergraph Partitioning
Yugao Zhu, Zhicheng Guo, Yuchao Wu +3
Hypergraph partitioning is a critical step in the design of complex embedded systems, essential for optimizing task mapping on heterogeneous MPSoCs and enabling multi-FPGA prototyp…
IMPart: Integration of Memetic Operations into Multi-Level Framework for Large-k-Way Hypergraph Partitioning
Yugao Zhu, Zhicheng Guo, Shang Liu +3
The problem of k-way hypergraph partitioning is fundamental with significant applications in various fields, including VLSI design and scientific computing. State-of-the-art hyperg…
ICP: Exploiting Instruction Correlation for Prefetching Irregular Memory Accesses
Mengming Li, Chenlu Miao, Buqing Xu +7
Irregular memory accesses pose challenges for effective and efficient data prefetching. While temporal prefetchers have recently shown promise for irregular memory access patterns,…
ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework
Qijun Zhang, Shang Liu, Yao Lu +2
Power is a primary objective in modern processor design, requiring accurate yet efficient power modeling techniques. Architecture-level power models are necessary for early power o…
ArchPower: Dataset for Architecture-Level Power Modeling of Modern CPU Design
Qijun Zhang, Yao Lu, Mengming Li +2
Power is the primary design objective of large-scale integrated circuits (ICs), especially for complex modern processors (i.e., CPUs). Accurate CPU power evaluation requires design…
AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decoupling
Qijun Zhang, Yao Lu, Mengming Li +1
Power efficiency is a critical design objective in modern CPU design. Architects need a fast yet accurate architecture-level power evaluation tool to perform early-stage power esti…
Profile-Guided Temporal Prefetching
Mengming Li, Qijun Zhang, Yichuan Gao +4
Temporal prefetching shows promise for handling irregular memory access patterns, which are common in data-dependent and pointer-based data structures. Recent studies introduced on…
Integrating Prefetcher Selection with Dynamic Request Allocation Improves Prefetching Efficiency
Mengming Li, Qijun Zhang, Yongqing Ren +1
Hardware prefetching plays a critical role in hiding the off-chip DRAM latency. The complexity of applications results in a wide variety of memory access patterns, prompting the de…
AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
Zhiyuan Yan, Wenji Fang, Mengming Li +4
Assertion-based verification (ABV) is a critical method to ensure logic designs comply with their architectural specifications. ABV requires assertions, which are generally convert…
FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modeling
Qijun Zhang, Mengming Li, Yao lu +1
Power efficiency is a critical design objective in modern processor design. A high-fidelity architecture-level power modeling method is greatly needed by CPU architects for guiding…
AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs
Wenji Fang, Mengming Li, Min Li +4
Assertion-based verification (ABV) is a critical method for ensuring design circuits comply with their architectural specifications, which are typically described in natural langua…
SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
Mengming Li, Wenji Fang, Qijun Zhang +1
The development of architecture specifications is an initial and fundamental stage of the integrated circuit (IC) design process. Traditionally, architecture specifications are cra…