95 citations · 118 across the 20 of their papers we have counts for
21 papers
Memory Compression for High-Fanout Agent Sandboxes
Mengming Li, Ceyu XU, Qijun Zhang +4
High-fanout agent workloads create a growing memory bottleneck because a single task may spawn many concurrent sandbox sessions. Yet these sandboxes are far from independent: they…
COOL: A Cooling-Aware Point Transformer Framework for Thermal Prediction in Advanced 3D/3.5D IC Packaging
Yao Lu, Zhicheng Guo, Qijun Zhang +4
Advanced 3D and 3.5D IC packaging significantly improves integration density but elevates thermal management challenges due to cross-layer heat coupling and complex cooling structu…
FSGen: Agile Fused and Sparse Accelerator Generator with Accurate Power Model for LLM Applications
Jay Zhe-An Mok, Qijun Zhang, Zhiyao Xie
With the growing demand of artificial intelligence (AI) applications, large language models (LLMs) have become important workloads in many domains. The question of how to efficient…
G-Power: Architecture-level GPU Power Modeling with Aggregated Knowledge Foundations from Known GPUs
Qijun Zhang, Yao Lu, Shang Liu +4
Graphics Processing Units (GPUs) have been serving as critical computation resources for large-scale parallel computations. With increasing chip complexity, power efficiency has be…
ICP: Exploiting Instruction Correlation for Prefetching Irregular Memory Accesses
Mengming Li, Chenlu Miao, Buqing Xu +7
Irregular memory accesses pose challenges for effective and efficient data prefetching. While temporal prefetchers have recently shown promise for irregular memory access patterns,…
MoE-Hub: Taming Software Complexity for Seamless MoE Overlap with Hardware-Accelerated Communication on Multi-GPU Systems
Zhuoshan Zhou, Chen Zhang, Shuyi Zhang +10
The Mixture-of-Experts (MoE) architecture is crucial for scaling large language models, but its scalability is severely limited by inter-GPU communication bottlenecks in multi-GPU…
Accelerating MoE with Dynamic In-Switch Computing on Multi-GPUs
Qijun Zhang, Chen Zhang, Zhuoshan Zhou +10
Mixture-of-Experts (MoE) has been adopted by many leading large models to reduce computational requirements. However, frequent inter-GPU communication in MoE expert parallelism (EP…
A New Benchmark for the Appropriate Evaluation of RTL Code Optimization
Yao Lu, Shang Liu, Hangan Zhou +3
The rapid progress of artificial intelligence increasingly relies on efficient integrated circuit (IC) design. Recent studies have explored the use of large language models (LLMs)…
ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework
Qijun Zhang, Shang Liu, Yao Lu +2
Power is a primary objective in modern processor design, requiring accurate yet efficient power modeling techniques. Architecture-level power models are necessary for early power o…
ArchPower: Dataset for Architecture-Level Power Modeling of Modern CPU Design
Qijun Zhang, Yao Lu, Mengming Li +2
Power is the primary design objective of large-scale integrated circuits (ICs), especially for complex modern processors (i.e., CPUs). Accurate CPU power evaluation requires design…
ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis
Wenkai Li, Yao Lu, Wenji Fang +3
Accurate power prediction in VLSI design is crucial for effective power optimization, especially as designs get transformed from gate-level netlist to layout stages. However, tradi…
AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decoupling
Qijun Zhang, Yao Lu, Mengming Li +1
Power efficiency is a critical design objective in modern CPU design. Architects need a fast yet accurate architecture-level power evaluation tool to perform early-stage power esti…
Profile-Guided Temporal Prefetching
Mengming Li, Qijun Zhang, Yichuan Gao +4
Temporal prefetching shows promise for handling irregular memory access patterns, which are common in data-dependent and pointer-based data structures. Recent studies introduced on…
Integrating Prefetcher Selection with Dynamic Request Allocation Improves Prefetching Efficiency
Mengming Li, Qijun Zhang, Yongqing Ren +1
Hardware prefetching plays a critical role in hiding the off-chip DRAM latency. The complexity of applications results in a wide variety of memory access patterns, prompting the de…
FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modeling
Qijun Zhang, Mengming Li, Yao lu +1
Power efficiency is a critical design objective in modern processor design. A high-fidelity architecture-level power modeling method is greatly needed by CPU architects for guiding…
Pointer: An Energy-Efficient ReRAM-based Point Cloud Recognition Accelerator with Inter-layer and Intra-layer Optimizations
Qijun Zhang, Zhiyao Xie
Point cloud is an important data structure for a wide range of applications, including robotics, AR/VR, and autonomous driving. To process the point cloud, many deep-learning-based…
SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
Mengming Li, Wenji Fang, Qijun Zhang +1
The development of architecture specifications is an initial and fundamental stage of the integrated circuit (IC) design process. Traditionally, architecture specifications are cra…
PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions
Qijun Zhang, Shiyu Li, Guanglei Zhou +4
Power efficiency is a critical design objective in modern microprocessor design. To evaluate the impact of architectural-level design decisions, an accurate yet efficient architect…
RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution
Shang Liu, Wenji Fang, Yao Lu +3
The automatic generation of RTL code (e.g., Verilog) using natural language instructions and large language models (LLMs) has attracted significant research interest recently. Howe…
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
Wenji Fang, Yao Lu, Shang Liu +5
In modern VLSI design flow, the register-transfer level (RTL) stage is a critical point, where designers define precise design behavior with hardware description languages (HDLs) l…
RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model
Yao Lu, Shang Liu, Qijun Zhang +1
Inspired by the recent success of large language models (LLMs) like ChatGPT, researchers start to explore the adoption of LLMs for agile hardware design, such as generating design…