95 citations · 108 across the 20 of their papers we have counts for
14 papers · 1 filter
FABO: Agent-Guided Discovery of Joint Breakpoint Optimization for Timing-Driven Routing Trees
Shang Liu, Wenji Fang, Jing Wang +3
The topology of a routing tree determines how a multi-pin net branches and shares physical wire, directly affecting wirelength, congestion, capacitance, and delay. We study a centr…
G-Power: Architecture-level GPU Power Modeling with Aggregated Knowledge Foundations from Known GPUs
Qijun Zhang, Yao Lu, Shang Liu +4
Graphics Processing Units (GPUs) have been serving as critical computation resources for large-scale parallel computations. With increasing chip complexity, power efficiency has be…
RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigm
Ziyan Guo, Wenji Fang, Wenkai Li +3
Accurate timing prediction at the register-transfer level (RTL) is a longstanding challenge in design automation. Existing graph-based methods struggle with limited receptive field…
IMPart: Integration of Memetic Operations into Multi-Level Framework for Large-k-Way Hypergraph Partitioning
Yugao Zhu, Zhicheng Guo, Shang Liu +3
The problem of k-way hypergraph partitioning is fundamental with significant applications in various fields, including VLSI design and scientific computing. State-of-the-art hyperg…
ICP: Exploiting Instruction Correlation for Prefetching Irregular Memory Accesses
Mengming Li, Chenlu Miao, Buqing Xu +7
Irregular memory accesses pose challenges for effective and efficient data prefetching. While temporal prefetchers have recently shown promise for irregular memory access patterns,…
ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework
Qijun Zhang, Shang Liu, Yao Lu +2
Power is a primary objective in modern processor design, requiring accurate yet efficient power modeling techniques. Architecture-level power models are necessary for early power o…
ArchPower: Dataset for Architecture-Level Power Modeling of Modern CPU Design
Qijun Zhang, Yao Lu, Mengming Li +2
Power is the primary design objective of large-scale integrated circuits (ICs), especially for complex modern processors (i.e., CPUs). Accurate CPU power evaluation requires design…
CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design
Wenji Fang, Shang Liu, Jing Wang +1
The rapid advancements of AI rely on the support of ICs. However, the growing complexity of digital ICs makes the traditional IC design process costly and time-consuming. In recent…
NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph
Wenji Fang, Wenkai Li, Shang Liu +3
Circuit representation learning has shown promise in advancing Electronic Design Automation (EDA) by capturing structural and functional circuit properties for various tasks. Exist…
A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA
Wenji Fang, Jing Wang, Yao Lu +4
Artificial intelligence (AI)-driven electronic design automation (EDA) techniques have been extensively explored for VLSI circuit design applications. Most recently, foundation AI…
AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
Zhiyuan Yan, Wenji Fang, Mengming Li +4
Assertion-based verification (ABV) is a critical method to ensure logic designs comply with their architectural specifications. ABV requires assertions, which are generally convert…
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
Wenji Fang, Shang Liu, Hongce Zhang +1
In digital IC design, compared with post-synthesis netlists or layouts, the early register-transfer level (RTL) stage offers greater optimization flexibility for both designers and…
AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs
Wenji Fang, Mengming Li, Min Li +4
Assertion-based verification (ABV) is a critical method for ensuring design circuits comply with their architectural specifications, which are typically described in natural langua…
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
Wenji Fang, Yao Lu, Shang Liu +5
In modern VLSI design flow, the register-transfer level (RTL) stage is a critical point, where designers define precise design behavior with hardware description languages (HDLs) l…