activity
20242026
most citedComprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification

1 citations · 1 across the 13 of their papers we have counts for

collaborators
Showing cs.ARShow all

7 papers · 1 filter

cs.AR2026

Agentic Hardware Design as Repository-Level Code Evolution

Cunxi Yu, Chenhui Deng, Nathaniel Pinckney +1

We present HORIZON, a self-evolving agent framework that treats hardware design as repository-level code evolution. A Markdown harness is compiled into a project pack containing do…

cs.AR2026

AUTOGATE: Automated Clock Gating via Toggling-Aware LLM-based RTL Rewriting

Yiting Wang, Chenhui Deng, Chia-Tung Ho +6

Fine-grain clock gating (FGCG) is among the most effective techniques for reducing dynamic power, yet current FGCG optimization flows remain largely manual. Recent LLM-based RTL op…

cs.AR2026

ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs

Chenhui Deng, Zhongzhi Yu, Guan-Ting Liu +3

Recent advances in LLMs have sparked growing interest in applying them to hardware design automation, particularly for accurate RTL code generation. Prior efforts follow two largel…

cs.AR2026

GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generation

Dimple Vijay Kochar, Nathaniel Pinckney, Guan-Ting Liu +4

RTL design often relies heavily on ad-hoc testbench creation early in the design cycle. While large language models (LLMs) show promise for RTL code generation, their ability to re…

cs.AR2025

ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generation

Chenhui Deng, Yun-Da Tsai, Guan-Ting Liu +2

Recent advances in large language models (LLMs) have enabled near-human performance on software coding benchmarks, but their effectiveness in RTL code generation remains limited du…

cs.AR2025

Marco: Configurable Graph-Based Task Solving and Multi-AI Agents Framework for Hardware Design

Chia-Tung Ho, Jing Gong, Yunsheng Bai +3

Hardware design presents numerous challenges stemming from its complexity and advancing technologies. These challenges result in longer turn-around-time (TAT) for optimizing perfor…

cs.AR2024

ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic Interpolation

Chenhui Deng, Yunsheng Bai, Haoxing Ren

Recent advancements in large language models (LLMs) have expanded their application across various domains, including chip design, where domain-adapted chip models like ChipNeMo ha…