6 citations · 13 across the 22 of their papers we have counts for
22 papers
PlaceReasoner-Beta: Reasoning-Driven Macro Placement and Benchmarking
Qiufeng Li, Chengxuan Wang, Rongqian Chen +6
Automated macro placement remains a fundamental challenge in VLSI physical design. Despite decades of research, existing approaches predominantly optimize hand-crafted proxy object…
CHORUS: Complementary Experts for High-Coverage Testbench Stimulus Generation
Hejia Zhang, Sheng Lu, Zhongming Yu +3
Large language models (LLMs) have advanced code generation, where executable feedback provides a more reliable learning signal than textual imitation alone. Hardware verification i…
SCALE: Self-Supervised Constraint-Aware Layout GEneration for Local P&R DRV Fixing at Advanced Nodes
Chia-Tung Ho, Haoyu Yang, Guanglei Zhou +6
As semiconductor manufacturing advances toward sub-2nm nodes, local place-and-route (P&R) design-rule violation (DRV) fixing is increasingly limited by complex rule interactions, d…
EvoDRC: A Self-Evolving Agentic Framework for Automated DRC Violation Repair
Bing-Yue Wu, Chia-Tung Ho, Haoyu Yang +2
Design rule check (DRC) closure remains a major bottleneck in advanced-node physical design. Although detailed routers are rule-aware, residual design rule violations (DRVs) often…
AUTOGATE: Automated Clock Gating via Toggling-Aware LLM-based RTL Rewriting
Yiting Wang, Chenhui Deng, Chia-Tung Ho +6
Fine-grain clock gating (FGCG) is among the most effective techniques for reducing dynamic power, yet current FGCG optimization flows remain largely manual. Recent LLM-based RTL op…
PDAGENT-BENCH: Characterizing, Grounding, and Architecting LLM/VLM Agents for VLSI Physical Design
Qiufeng Li, Rongqian Chen, Quan Cheng +6
Large Language Models and vision-language models have shown remarkable success in the front-end design of Very Large-Scale Integrated Circuits, yet their capabilities for VLSI phys…
TOPCELL: Topology Optimization of Standard Cell via LLMs
Zhan Song, Yu-Tung Liu, Chen Chen +6
Transistor topology optimization is a critical step in standard cell design, directly dictating diffusion sharing efficiency and downstream routability. However, identifying optima…
FVRuleLearner: Operator-Level Reasoning Tree (Op-Tree)-Based Rules Learning for Formal Verification
Lily Jiaxin Wan, Chia-Tung Ho, Yunsheng Bai +4
The remarkable reasoning and code generation capabilities of large language models (LLMs) have recently motivated increasing interest in automating formal verification (FV), a proc…
LLM4Cov: Execution-Aware Agentic Learning for High-coverage Testbench Generation
Hejia Zhang, Zhongming Yu, Chia-Tung Ho +3
Execution-aware LLM agents offer a promising paradigm for learning from tool feedback, but such feedback can be expensive and slow to obtain, making online reinforcement learning (…
GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generation
Dimple Vijay Kochar, Nathaniel Pinckney, Guan-Ting Liu +4
RTL design often relies heavily on ad-hoc testbench creation early in the design cycle. While large language models (LLMs) show promise for RTL code generation, their ability to re…
HeaRT: A Hierarchical Circuit Reasoning Tree-Based Agentic Framework for AMS Design Optimization
Souradip Poddar, Chia-Tung Ho, Ziming Wei +3
Conventional AI-driven AMS design automation algorithms remain constrained by their reliance on high-quality datasets to capture underlying circuit behavior, coupled with poor tran…
FVDebug: An LLM-Driven Debugging Assistant for Automated Root Cause Analysis of Formal Verification Failures
Yunsheng Bai, Ghaith Bany Hamad, Chia-Tung Ho +2
Debugging formal verification (FV) failures represents one of the most time-consuming bottlenecks in modern hardware design workflows. When properties fail, engineers must manually…
Autonomous Code Evolution Meets NP-Completeness
Cunxi Yu, Rongjian Liang, Chia-Tung Ho +1
Large language models (LLMs) have recently shown strong coding abilities, enabling not only static code generation but also iterative code self-evolving through agentic frameworks.…
SchemaCoder: Automatic Log Schema Extraction Coder with Residual Q-Tree Boosting
Lily Jiaxin Wan, Chia-Tung Ho, Rongjian Liang +3
Log schema extraction is the process of deriving human-readable templates from massive volumes of log data, which is essential yet notoriously labor-intensive. Recent studies have…
Polymath: A Self-Optimizing Agent with Dynamic Hierarchical Workflow
Chia-Tung Ho, Jing Gong, Xufeng Yao +3
Large language models (LLMs) excel at solving complex tasks by executing agentic workflows composed of detailed instructions and structured operations. Yet, building general-purpos…
Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
Nathaniel Pinckney, Chenhui Deng, Chia-Tung Ho +5
We present the Comprehensive Verilog Design Problems (CVDP) benchmark, a new dataset and infrastructure to advance LLM and agent research in hardware design and verification. CVDP…
PRO-V-R1: Reasoning Enhanced Programming Agent for RTL Verification
Yujie Zhao, Zhijing Wu, Boqin Yuan +6
Register-Transfer Level (RTL) verification is a primary bottleneck, consuming 60-70% of development time. While Large Language Models (LLMs) show promise for RTL automation, their…
Timing Analysis Agent: Autonomous Multi-Corner Multi-Mode (MCMM) Timing Debugging with Timing Debug Relation Graph
Jatin Nainani, Chia-Tung Ho, Anirudh Dhurka +1
Timing analysis is an essential and demanding verification method for Very Large Scale Integrated (VLSI) circuit design and optimization. In addition, it also serves as the corners…
Marco: Configurable Graph-Based Task Solving and Multi-AI Agents Framework for Hardware Design
Chia-Tung Ho, Jing Gong, Yunsheng Bai +3
Hardware design presents numerous challenges stemming from its complexity and advancing technologies. These challenges result in longer turn-around-time (TAT) for optimizing perfor…
DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agent
Chen-Chia Chang, Chia-Tung Ho, Yaguang Li +2
In the advanced technology nodes, the integrated design rule checker (DRC) is often utilized in place and route tools for fast optimization loops for power-performance-area. Implem…
VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool
Chia-Tung Ho, Haoxing Ren, Brucek Khailany
Due to the growing complexity of modern Integrated Circuits (ICs), automating hardware design can prevent a significant amount of human error from the engineering process and resul…
Large Language Model (LLM) for Standard Cell Layout Design Optimization
Chia-Tung Ho, Haoxing Ren
Standard cells are essential components of modern digital circuit designs. With process technologies advancing toward 2nm, more routability issues have arisen due to the decreasing…