6 citations · 7 across the 9 of their papers we have counts for
10 papers
GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generation
Dimple Vijay Kochar, Nathaniel Pinckney, Guan-Ting Liu +4
RTL design often relies heavily on ad-hoc testbench creation early in the design cycle. While large language models (LLMs) show promise for RTL code generation, their ability to re…
FVDebug: An LLM-Driven Debugging Assistant for Automated Root Cause Analysis of Formal Verification Failures
Yunsheng Bai, Ghaith Bany Hamad, Chia-Tung Ho +2
Debugging formal verification (FV) failures represents one of the most time-consuming bottlenecks in modern hardware design workflows. When properties fail, engineers must manually…
Autonomous Code Evolution Meets NP-Completeness
Cunxi Yu, Rongjian Liang, Chia-Tung Ho +1
Large language models (LLMs) have recently shown strong coding abilities, enabling not only static code generation but also iterative code self-evolving through agentic frameworks.…
SchemaCoder: Automatic Log Schema Extraction Coder with Residual Q-Tree Boosting
Lily Jiaxin Wan, Chia-Tung Ho, Rongjian Liang +3
Log schema extraction is the process of deriving human-readable templates from massive volumes of log data, which is essential yet notoriously labor-intensive. Recent studies have…
Polymath: A Self-Optimizing Agent with Dynamic Hierarchical Workflow
Chia-Tung Ho, Jing Gong, Xufeng Yao +3
Large language models (LLMs) excel at solving complex tasks by executing agentic workflows composed of detailed instructions and structured operations. Yet, building general-purpos…
Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
Nathaniel Pinckney, Chenhui Deng, Chia-Tung Ho +5
We present the Comprehensive Verilog Design Problems (CVDP) benchmark, a new dataset and infrastructure to advance LLM and agent research in hardware design and verification. CVDP…