activity
20232026
collaborators

7 papers

cs.AR2026

FlexLLM: Composable HLS Library for Flexible Hybrid LLM Accelerator Design

Jiahao Zhang, Zifan He, Nicholas Fraser +3

We present FlexLLM, a composable High-Level Synthesis (HLS) library for rapid development of domain-specific LLM accelerators. FlexLLM exposes key architectural degrees of freedom…

cs.AR2025

SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators

Yaman Umuroglu, Christoph Berganski, Felix Jentzsch +8

While neural network quantization effectively reduces the cost of matrix multiplications, aggressive quantization can expose non-matrix-multiply operations as significant performan…

cs.LG2025

FINN-GL: Generalized Mixed-Precision Extensions for FPGA-Accelerated LSTMs

Shashwat Khandelwal, Jakoba Petri-Koenig, Thomas B. Preußer +2

Recurrent neural networks (RNNs), particularly LSTMs, are effective for time-series tasks like sentiment analysis and short-term stock prediction. However, their computational comp…

cs.LG2025

Improving Quantization with Post-Training Model Expansion

Giuseppe Franco, Pablo Monteagudo-Lago, Ian Colbert +2

The size of a model has been a strong predictor of its quality, as well as its cost. As such, the trade-off between model cost and quality has been well-studied. Post-training opti…

cs.DC2024

Optimizing Communication for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL

Marius Meyer, Tobias Kenter, Lucian Petrica +3

Most FPGA boards in the HPC domain are well-suited for parallel scaling because of the direct integration of versatile and high-throughput network ports. However, the utilization o…

cs.DC2023

ACCL+: an FPGA-Based Collective Engine for Distributed Applications

Zhenhao He, Dario Korolija, Yu Zhu +5

FPGAs are increasingly prevalent in cloud deployments, serving as Smart NICs or network-attached accelerators. Despite their potential, developing distributed FPGA-accelerated appl…

cs.CV2023

Shedding the Bits: Pushing the Boundaries of Quantization with Minifloats on FPGAs

Shivam Aggarwal, Hans Jakob Damsgaard, Alessandro Pappalardo +4

Post-training quantization (PTQ) is a powerful technique for model compression, reducing the numerical precision in neural networks without additional training overhead. Recent wor…