19 citations · 29 across the 9 of their papers we have counts for
10 papers
Error-Rate Reduction in LDPC Decoding via Bit-Aligned Temporal Reinforcement in Parallel Probabilistic-Bit Dynamics
Naoya Onizawa, Takahiro Hanyu
Probabilistic bits (p-bits) provide a physical and algorithmic primitive for stochastic inference, but highly parallel updates can alter their collective dynamics. We study the dec…
Differential Stochastic Simulated Annealing Processor for Fully Connected 2048-Spin Optimization
Naoya Onizawa, Md Mohaimenul Alam, Sean Smithson +2
A 2,048-spin fully connected annealing processor based on differential stochastic simulated annealing (DSSA) is presented as an architectural design in TSMC 28 nm CMOS with a 3 mm…
A Unified Performance-Cost Landscape of Parallel p-bit Ising Machines Based on Update Dynamics
Naoya Onizawa, Takahiro Hanyu
Parallel p-bit Ising machines are a promising platform for fast and energy-efficient combinatorial optimization, but their scalability depends on update synchronization, hardware d…
Efficient Few-Shot Learning for Edge AI via Knowledge Distillation on MobileViT
Shuhei Tsuyuki, Reda Bensaid, Jérémy Morlier +4
Efficient and adaptable deep learning models are an important area of deep learning research, driven by the need for highly efficient models on edge devices. Few-shot learning enab…
Scylla at APOGEE: The Impact of Starbursts on the Chemical Evolution of the Magellanic Clouds
Ivanna Escala, Kristen B. W. McQuinn, Sten Hasselquist +11
Owing to their proximity to the Milky Way, the Large and Small Magellanic Clouds (L/SMC) uniquely probe the evolution of low-mass galaxies undergoing mutual interactions. In this w…
Energy-Efficient p-Bit-Based Fully-Connected Quantum-Inspired Simulated Annealer with Dual BRAM Architecture
Naoya Onizawa, Taiga Kubuta, Duckgyu Shin +1
Probabilistic bits (p-bits) offer an energy-efficient hardware abstraction for stochastic optimization; however, existing p-bit-based simulated annealing accelerators suffer from p…
Bit-Width-Aware Design Environment for Few-Shot Learning on Edge AI Hardware
R. Kanda, H. L. Blevec, N. Onizawa +3
In this study, we propose an implementation methodology of real-time few-shot learning on tiny FPGA SoCs such as the PYNQ-Z1 board with arbitrary fixed-point bit-widths. Tensil-bas…
Design Environment of Quantization-Aware Edge AI Hardware for Few-Shot Learning
R. Kanda, N. Onizawa, M. Leonardon +2
This study aims to ensure consistency in accuracy throughout the entire design flow in the implementation of edge AI hardware for few-shot learning, by implementing fixed-point dat…
Enhanced Convergence in p-bit Based Simulated Annealing with Partial Deactivation for Large-Scale Combinatorial Optimization Problems
Naoya Onizawa, Takahiro Hanyu
This article critically investigates the limitations of the simulated annealing algorithm using probabilistic bits (pSA) in solving large-scale combinatorial optimization problems.…
GPU-accelerated simulated annealing based on p-bits with real-world device-variability modeling
Naoya Onizawa, Takahiro Hanyu
Probabilistic computing using probabilistic bits (p-bits) presents an efficient alternative to traditional CMOS logic for complex problem-solving, including simulated annealing and…