activity
20232026
most citedPhysically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement

7 citations · 8 across the 10 of their papers we have counts for

collaborators

11 papers

eess.SY2026

AutoDRI: Bridging the Semantic Gap for Automated Design Rule Integration in CP-SAT-Based Cell Synthesis under Multi-Patterning

Yuhao Ren, Yucheng Wang, Zihao Chen +2

Design-rule integration (DRI) remains a major bottleneck for scalable (Constraint Programming with SAT) CP-SAT-based standard cell synthesis and rapid technology enablement at adva…

cs.AR2026

PACT: Post-route Agentic Checkpoint Tuning for FPGA Timing Closure

Huan Lin, Kunlong Li, Lingli Wang +1

Late-stage FPGA timing closure often starts from an implemented design whose remaining violations are visible in timing reports. Engineering change order (ECO) optimization is a st…

cs.AR2026

From Tool Invocation to Source-Mechanism Exploration: Protected White-Box DSE for Open-Source EDA

Zhiyu Zheng, Yiming Du, Ziyi Wang +1

Open-source EDA tools allow design-space exploration (DSE) to move beyond public knobs and into bounded source-level mechanisms inside staged optimizers. We present ReviewDSE, a pr…

cs.AR2026

GoalEvolve: From Handcrafted Algorithm Priors to Goal-Driven Evolution of Physical Design Algorithms

Haixu Liu, Lei Zhou, Yuhao Ren +2

Physical design algorithms operate within tightly coupled, multi-stage optimization flows, where stage-local gains may vanish or induce downstream degradation. Existing program-evo…

eess.SY2026

Invited: Toward Sustainable and Transparent Benchmarking for Academic Physical Design Research

Liwen Jiang, Andrew B. Kahng, Zhiang Wang +1

This paper presents RosettaStone 2.0, an open benchmark translation and evaluation framework built on OpenROAD-Research. RosettaStone 2.0 provides complete RTL-to-GDS reference flo…

eess.SP2025

Bridging the Initialization Gap: A Co-Optimization Framework for Mixed-Size Global Placement

Yuhao Ren, Yiting Liu, Yanfei Zhou +4

Global placement is a critical step with high computational complexity in VLSI physical design. Modern analytical placers formulate the placement problem as a nonlinear optimizatio…