5 citations · 9 across the 38 of their papers we have counts for
15 papers · 1 filter
ARMOR: Accelerating RTL Simulation by Mitigating the Front-End Bottleneck Using Node Compression
Jiaping Tang, Jianan Mu, Zhiteng Chao +3
RTL simulation is indispensable in chip design. High-performance simulators typically lower each node in the RTL graph into an instruction sequence. Although this per-node lowering…
An Efficient Fault-Tolerance Scheme for CKKS Computation on CPUs
Jianan Mu, Ge Yu, Tenghui Hua +6
Fully homomorphic encryption (FHE) enables computation on encrypted data, but its long ciphertext dataflow and high-dimensional modular arithmetic make it vulnerable to silent data…
Rtl2lean: Automated RTL-to-Lean Translation with Hierarchical Theorem Generation and Lemma Reuse
Hongqin Lyu, Junxing Dong, Yonghao Wang +3
Formal verification with interactive theorem provers can provide strong correctness guarantees for register transfer level designs, but applying it to existing SystemVerilog code r…
Harvesting AI Computation at the Edge via Generic Approximation
Yihan Wang, Huiru Yan, Luxin Zhang +6
With the widespread adoption of AI in various IoT scenarios such as smart sensing and processing, AI chips have become a common component at the edge. These chips are typically spe…
VeriPilot: An LLM-Powered Verilog Debugging Framework
Yihan Wang, Cheng Liu, Jiazheng Zhang +4
Verilog debugging remains one of the most time-consuming stages in digital circuit design. Recent advances in Large Language Models (LLMs) have enabled automated debugging; however…
FT-Pilot: Automated Fault-Tolerant RTL Rewriting via Vulnerability-Guided LLMs
Weixing Liu, Zizhen Liu, Jing Ye +4
As integrated circuit technologies continue to scale toward advanced process nodes, the continual reduction in node capacitance and supply voltage has made digital systems increasi…
Arcane: An Assertion Reduction Framework through Semantic Clustering and MCTS-Guided Rule Exploring
Hongqin Lyu, Yonghao Wang, Zhiteng Chao +2
Assertion-based Verification (ABV) is essential for ensuring that hardware designs conform to their intended specifications. However, existing automated assertion-generation approa…
Pecker: Bug Localization Framework for Sequential Designs via Causal Chain Reconstruction
Jiaping Tang, Jianan Mu, Tianyun Ma +3
Debugging represents a time-consuming and labor-intensive task in hardware design, with bug localization constituting a substantial portion of this process. While spectrum-based bu…
CoverAssert: Iterative LLM Assertion Generation Driven by Functional Coverage via Syntax-Semantic Representations
Yonghao Wang, Yang Yin, Hongqin Lyu +8
LLMs can generate SystemVerilog assertions (SVAs) from natural language specs, but single-pass outputs often lack functional coverage due to limited IC design understanding. We pro…
From Indiscriminate to Targeted: Functionally Critical Signal-Driven Assertion Generation using LLMs for Efficient RTL Verification
Yonghao Wang, Hongqin Lyu, Boling Chen +9
Functional verification has become the most time-consuming phase in IC development, and Assertion-Based Verification (ABV) is key to reducing debugging time. However, existing LLM-…
RTLSeek: Boosting the LLM-Based RTL Generation with Multi-Stage Diversity-Oriented Reinforcement Learning
Xinyu Zhang, Zhiteng Chao, Yonghao Wang +6
Register Transfer Level (RTL) design translates high-level specifications into hardware using HDLs such as Verilog. Although LLM-based RTL generation is promising, the scarcity of…
On the Vulnerability of FHE Computation to Silent Data Corruption
Jianan Mu, Ge Yu, Zhaoxuan Kan +6
Fully Homomorphic Encryption (FHE) is rapidly emerging as a promising foundation for privacy-preserving cloud services, enabling computation directly on encrypted data. As FHE impl…
Iterative LLM-Based Assertion Generation Using Syntax-Semantic Representations for Functional Coverage-Guided Verification
Yonghao Wang, Jiaxin Zhou, Yang Yin +6
While leveraging LLMs to automatically generate SystemVerilog assertions (SVAs) from natural language specifications holds great potential, existing techniques face a key challenge…
From Buffers to Registers: Unlocking Fine-Grained FlashAttention with Hybrid-Bonded 3D NPU Co-Design
Jinxin Yu, Yudong Pan, Mengdi Wang +4
Transformer-based models dominate modern AI workloads but exacerbate memory bottlenecks due to their quadratic attention complexity and ever-growing model sizes. Existing accelerat…
Lifecycle Cost-Effectiveness Modeling for Redundancy-Enhanced Multi-Chiplet Architectures
Zizhen Liu, Fangzhiyi Wang, Mengdi Wang +4
The growing demand for compute-intensive applications has made multi-chiplet architectures a promising alternative to monolithic designs, offering improved scalability and manufact…