5 citations · 9 across the 36 of their papers we have counts for
30 papers · 1 filter
ARMOR: Accelerating RTL Simulation by Mitigating the Front-End Bottleneck Using Node Compression
Jiaping Tang, Jianan Mu, Zhiteng Chao +3
RTL simulation is indispensable in chip design. High-performance simulators typically lower each node in the RTL graph into an instruction sequence. Although this per-node lowering…
An Efficient Fault-Tolerance Scheme for CKKS Computation on CPUs
Jianan Mu, Ge Yu, Tenghui Hua +6
Fully homomorphic encryption (FHE) enables computation on encrypted data, but its long ciphertext dataflow and high-dimensional modular arithmetic make it vulnerable to silent data…
Rtl2lean: Automated RTL-to-Lean Translation with Hierarchical Theorem Generation and Lemma Reuse
Hongqin Lyu, Junxing Dong, Yonghao Wang +3
Formal verification with interactive theorem provers can provide strong correctness guarantees for register transfer level designs, but applying it to existing SystemVerilog code r…
Harvesting AI Computation at the Edge via Generic Approximation
Yihan Wang, Huiru Yan, Luxin Zhang +6
With the widespread adoption of AI in various IoT scenarios such as smart sensing and processing, AI chips have become a common component at the edge. These chips are typically spe…
VeriPilot: An LLM-Powered Verilog Debugging Framework
Yihan Wang, Cheng Liu, Jiazheng Zhang +4
Verilog debugging remains one of the most time-consuming stages in digital circuit design. Recent advances in Large Language Models (LLMs) have enabled automated debugging; however…
FT-Pilot: Automated Fault-Tolerant RTL Rewriting via Vulnerability-Guided LLMs
Weixing Liu, Zizhen Liu, Jing Ye +4
As integrated circuit technologies continue to scale toward advanced process nodes, the continual reduction in node capacitance and supply voltage has made digital systems increasi…