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20212026
most citedSASH: Efficient Secure Aggregation Based on SHPRG For Federated Learning

2 citations · 2 across the 11 of their papers we have counts for

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cs.AR2026

FT-Pilot: Automated Fault-Tolerant RTL Rewriting via Vulnerability-Guided LLMs

Weixing Liu, Zizhen Liu, Jing Ye +4

As integrated circuit technologies continue to scale toward advanced process nodes, the continual reduction in node capacitance and supply voltage has made digital systems increasi…

cs.AR2026

Lifecycle Cost-Effectiveness Modeling for Redundancy-Enhanced Multi-Chiplet Architectures

Zizhen Liu, Fangzhiyi Wang, Mengdi Wang +4

The growing demand for compute-intensive applications has made multi-chiplet architectures a promising alternative to monolithic designs, offering improved scalability and manufact…

cs.AR2025

Analysis of LLM Vulnerability to GPU Soft Errors: An Instruction-Level Fault Injection Study

Duo Chai, Zizhen Liu, Shuhuai Wang +4

Large language models (LLMs) are highly compute- and memory-intensive, posing significant demands on high-performance GPUs. At the same time, advances in GPU technology driven by s…

cs.AR2025

InF-ATPG: Intelligent FFR-Driven ATPG with Advanced Circuit Representation Guided Reinforcement Learning

Bin Sun, Rengang Zhang, Zhiteng Chao +4

Automatic test pattern generation (ATPG) is a crucial process in integrated circuit (IC) design and testing, responsible for efficiently generating test patterns. As semiconductor…

cs.AR2025

RIROS: A Parallel RTL Fault SImulation FRamework with TwO-Dimensional Parallelism and Unified Schedule

Jiaping Tang, Jianan Mu, Zizhen Liu +6

With the rapid development of safety-critical applications such as autonomous driving and embodied intelligence, the functional safety of the corresponding electronic chips becomes…

cs.AR2025

Extend IVerilog to Support Batch RTL Fault Simulation

Jiaping Tang, Jianan Mu, Zizhen Liu +3

The advancement of functional safety has made RTL-level fault simulation increasingly important to achieve iterative efficiency in the early stages of design and to ensure complian…

cs.AR2025

ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy

Jiaping Tang, Jianan Mu, Silin Liu +8

As intelligent computing devices increasingly integrate into human life, ensuring the functional safety of the corresponding electronic chips becomes more critical. A key metric fo…