2 papers
cs.AR2026
SUSpMV: A High Frequency Sparse Matrix Vector Multiplier on HBM Enabled FPGA written in SUS
Lennart Van Hirtum, David Volz, Andreas Koch +1
SUSpMV is a Sparse Matrix Vector multiplication (SpMV) accelerator written in the upcoming HDL SUS. By leveraging SUS's unique latency counting and inference mechanism, SUSpMV coul…
cs.DB2026
Bringing Data Transformations Near-Memory for Low-Latency Analytics in HTAP Environments
Arthur Bernhardt, David Volz, Sajjad Tamimi +2
In this paper we propose an approach for executing data transformations near- or in-storage on intelligent storage systems. The currently prevailing approach of extracting the data…