9 citations · 16 across the 9 of their papers we have counts for
9 papers
SysFuSS: System-Level Firmware Fuzzing with Selective Symbolic Execution
Dakshina Tharindu, Aruna Jayasena, Prabhat Mishra
Firmware serves as the critical interface between hardware and software in computing systems, making any bugs or vulnerabilities particularly dangerous as they can cause catastroph…
Application-Specific Power Side-Channel Attacks and Countermeasures: A Survey
Sahan Sanjaya, Aruna Jayasena, Prabhat Mishra
Side-channel attacks try to extract secret information from a system by analyzing different side-channel signatures, such as power consumption, electromagnetic emanation, thermal d…
Towards a Functionally Complete and Parameterizable TFHE Processor
Valentin Reyes Häusler, Gabriel Ott, Aruna Jayasena +1
Fully homomorphic encryption allows the evaluation of arbitrary functions on encrypted data. It can be leveraged to secure outsourced and multiparty computation. TFHE is a fast tor…
SleepWalk: Exploiting Context Switching and Residual Power for Physical Side-Channel Attacks
Sahan Sanjaya, Aruna Jayasena, Prabhat Mishra
Context switching is utilized by operating systems to change the execution context between application programs. It involves saving and restoring the states of multiple registers a…
Information Leakage through Physical Layer Supply Voltage Coupling Vulnerability
Sahan Sanjaya, Aruna Jayasena, Prabhat Mishra
Side-channel attacks exploit variations in non-functional behaviors to expose sensitive information across security boundaries. Existing methods leverage side-channels based on pow…
TroLL: Exploiting Structural Similarities between Logic Locking and Hardware Trojans
Yuntao Liu, Aruna Jayasena, Prabhat Mishra +1
Logic locking and hardware Trojans are two fields in hardware security that have been mostly developed independently from each other. In this paper, we identify the relationship be…
HIVE: Scalable Hardware-Firmware Co-Verification using Scenario-based Decomposition and Automated Hint Extraction
Aruna Jayasena, Prabhat Mishra
Hardware-firmware co-verification is critical to design trustworthy systems. While formal methods can provide verification guarantees, due to the complexity of firmware and hardwar…
Sequence-Based Incremental Concolic Testing of RTL Models
Hasini Witharana, Aruna Jayasena, Prabhat Mishra
Concolic testing is a scalable solution for automated generation of directed tests for validation of hardware designs. Unfortunately, concolic testing also fails to cover complex c…
Design for Trust utilizing Rareness Reduction
Aruna Jayasena, Prabhat Mishra
Increasing design complexity and reduced time-to-market have motivated manufacturers to outsource some parts of the System-on-Chip (SoC) design flow to third-party vendors. This pr…