10 papers
NeuroAbs: A Neuro-Symbolic RTL Abstraction Framework for Property Checking Acceleration
Zhiyuan Yan, Xiaofeng Zhou, Ziyue Zheng +5
Formal verification is a crucial technique for ensuring the functional correctness of hardware designs. In the context of property checking, a key challenge is how to efficiently p…
MiCoPro: End-to-End Mixed Precision HW/SW Co-design with HW-aware Proxy Model
Zijun Jiang, Yangdi Lyu
Quantized Neural Networks~(QNN) with low-bitwidth data have proven promising in efficient storage and computation on edge devices. To mitigate accuracy degradation while maximizing…
ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation
Yan Tan, Jiping Du, Xiangchen Meng +1
Large language models have shown strong potential for Verilog RTL generation. However, many existing benchmarks are built from short, self-contained module-level tasks. These tasks…
HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing
Ya Wang, Hanwei Fan, Zhenguo Liu +4
Modern processor verification struggles to reach deep architectural states due to the inefficiencies of traditional mutation-based fuzzing. We propose HiFuzz, a novel hierarchical…
VerilogCL: A Contrastive Learning Framework for Robust LLM-Based Verilog Generation
Yan Tan, Tong Liu, Xiangchen Meng +1
Large Language Models (LLMs) have recently achieved strong performance in software code generation. However, applying them to hardware description languages (HDLs), such as Verilog…
AutoVeriFix+: High-Correctness RTL Generation via Trace-Aware Causal Fix and Semantic Redundancy Pruning
Yan Tan, Xiangchen Meng, Zijun Jiang +1
Large language models (LLMs) have demonstrated impressive capabilities in generating software code for high-level programming languages such as Python and C++. However, their appli…