12 papers
HINT: Toward an Executable Hardware-Intent Representation Layer for LLM-Driven RTL Generation
Tairan Cheng, Yi Liu, Dongsheng Zuo +6
Generating implementation-quality RTL with large language models (LLMs) remains difficult because direct generation must resolve microarchitecture while simultaneously producing an…
UniRTL: Unifying Code and Graph for Robust RTL Representation Learning
Yi Liu, Hongji Zhang, Lei Chen +2
Developing effective representations for register transfer level (RTL) designs is crucial for accelerating the hardware design workflow. Existing approaches, however, typically rel…
From Craft to Kernel: A Governance-First Execution Architecture and Semantic ISA for Agentic Computers
Xiangyu Wen, Yuang Zhao, Xiaoyu Xu +9
The transition of agentic AI from brittle prototypes to production systems is stalled by a pervasive crisis of craft. We suggest that the prevailing orchestration paradigm-delegati…
DiffHLS: Differential Learning for High-Level Synthesis QoR Prediction with GNNs and LLM Code Embeddings
Zedong Peng, Zeju Li, Qiang Xu +1
High-Level Synthesis (HLS) compiles C/C++ into RTL, but exploring pragma-driven optimization choices remains expensive because each design point requires time-consuming synthesis.…
FormalRTL: Verified RTL Synthesis at Scale
Kezhi Li, Min Li, Xiangyu Wen +4
Large language models (LLMs) have demonstrated significant potential in automating hardware synthesis, yet substantial barriers remain for industrial-scale, datapath-centric design…
CktEvo: Repository-Level RTL Code Benchmark for Design Evolution
Zhengyuan Shi, Jingxin Wang, Tairan Cheng +3
Register-Transfer Level (RTL) coding is an iterative, repository-scale process in which Power, Performance, and Area (PPA) emerge from interactions across many files and the downst…