14 papers
HINT: Toward an Executable Hardware-Intent Representation Layer for LLM-Driven RTL Generation
Tairan Cheng, Yi Liu, Dongsheng Zuo +6
Generating implementation-quality RTL with large language models (LLMs) remains difficult because direct generation must resolve microarchitecture while simultaneously producing an…
Miter-Aware LUT Mapping: Aligning Structure and Solvability for Efficient Logic Equivalence Checking
Jiaying Zhu, Zhengyuan Shi, Mengxia Tao +3
Logic Equivalence Checking (LEC), a fundamental hardware verification task, is often bottlenecked by synthesis-induced structural perturbations and XOR-dense regions that degrade S…
Rethinking Clause Management for CDCL SAT Solvers
Yalun Cai, Xindi Zhang, Zhengyuan Shi +2
Boolean Satisfiability (SAT) solving underpins a wide range of applications in Electronic Design Automation (EDA), particularly formal verification. However, this paper observes th…
CktEvo: Repository-Level RTL Code Benchmark for Design Evolution
Zhengyuan Shi, Jingxin Wang, Tairan Cheng +3
Register-Transfer Level (RTL) coding is an iterative, repository-scale process in which Power, Performance, and Area (PPA) emerge from interactions across many files and the downst…
GNN-based Path-aware multi-view Circuit Learning for Technology Mapping
Wentao Jiang, Jingxin Wang, Zhang Hu +5
Traditional technology mapping suffers from systemic inaccuracies in delay estimation due to its reliance on abstract, technology-agnostic delay models that fail to capture the nua…
Functional Matching of Logic Subgraphs: Beyond Structural Isomorphism
Ziyang Zheng, Kezhi Li, Zhengyuan Shi +1
Subgraph matching in logic circuits is foundational for numerous Electronic Design Automation (EDA) applications, including datapath optimization, arithmetic verification, and hard…