18 citations · 74 across the 14 of their papers we have counts for
16 papers
Scalable AXI4 Transaction Monitoring for Mixed-Criticality SoCs: From Phase-Level Precision to ID-Level Efficiency
Chaoqun Liang, Thomas Benz, Alessandro Ottaviano +4
Mixed-criticality Systems-on-Chip (SoCs) with on-chip interconnects based on the AXI4 open standard protocol lack a protocol-level timeout mechanism, exposing systems to deadlocks…
Assessing Triple Modular Redundancy for Wide-Link, Low-Latency NoC Routers: Reliability and Physical Design Challenges
Chen Wu, Michael Rogenmoser, Luca Benini +1
Protecting the Network-on-Chip (NoC) of physical-AI tile-based accelerators deployed in harsh environments against single-event effects (SEEs) is paramount for preventing NoC failu…
CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees
Lorenzo Leone, Philip Wiese, Gamze İslamoğlu +4
We present Chimera, a flexible and scalable Microcontroller Unit (MCU) designed to accelerate real-time inference of rapidly evolving transformer-based models at the ultra-low-powe…
Who Checks the Checker? Enhancing Component-level Architectural SEU Fault Tolerance for End-to-End SoC Protection
Michael Rogenmoser, Philippe Sauter, Chen Wu +2
Single-event upset (SEU) fault tolerance for systems-on-chip (SoCs) in radiation-heavy environments is often addressed by architectural fault-tolerance approaches protecting indivi…
A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
Thomas Benz, Axel Vanoni, Michael Rogenmoser +1
With the ever-growing heterogeneity in computing systems, driven by modern machine learning applications, pressure is increasing on memory systems to handle arbitrary and more dema…
relOBI: A Reliable Low-latency Interconnect for Tightly-Coupled On-chip Communication
Michael Rogenmoser, Angelo Garofalo, Luca Benini
On-chip communication is a critical element of modern systems-on-chip (SoCs), allowing processor cores to interact with memory and peripherals. Interconnects require special care i…
A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications
Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti +20
Next-generation mixed-criticality Systems-on-chip (SoCs) for robotics, automotive, and space must execute mixed-criticality AI-enhanced sensor processing and control workloads, ens…
FlooNoC: A 645 Gbps/link 0.15 pJ/B/hop Open-Source NoC with Wide Physical Links and End-to-End AXI4 Parallel Multi-Stream Support
Tim Fischer, Michael Rogenmoser, Thomas Benz +2
The new generation of domain-specific AI accelerators is characterized by rapidly increasing demands for bulk data transfers, as opposed to small, latency-critical cache line trans…
Trikarenos: Design and Experimental Characterization of a Fault-Tolerant 28nm RISC-V-based SoC
Michael Rogenmoser, Philip Wiese, Bruno Endres Forlin +5
RISC-V-based fault-tolerant system-on-chip (SoC) designs are critical for the new generation of automotive and space SoC architectures. However, reliability assessment requires cha…
SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications
Michael Rogenmoser, Alessandro Ottaviano, Thomas Benz +4
In the last decade, we have witnessed exponential growth in the complexity of control systems for safety-critical applications (automotive, robots, industrial automation) and their…
Trikarenos: A Fault-Tolerant RISC-V-based Microcontroller for CubeSats in 28nm
Michael Rogenmoser, Luca Benini
One of the key challenges when operating microcontrollers in harsh environments such as space is radiation-induced Single Event Upsets (SEUs), which can lead to errors in computati…
PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge
Vikram Jain, Matheus Cavalcante, Nazareno Bruschi +6
Emerging deep neural network (DNN) applications require high-performance multi-core hardware acceleration with large data bursts. Classical network-on-chips (NoCs) use serial packe…
FlooNoC: A Multi-Tbps Wide NoC for Heterogeneous AXI4 Traffic
Tim Fischer, Michael Rogenmoser, Matheus Cavalcante +2
Meeting the staggering bandwidth requirements of today's applications challenges the traditional narrow and serialized NoCs, which hit hard bounds on the maximum operating frequenc…
A High-performance, Energy-efficient Modular DMA Engine Architecture
Thomas Benz, Michael Rogenmoser, Paul Scheffler +5
Data transfers are essential in today's computing systems as latency and complex memory access patterns are increasingly challenging to manage. Direct memory access engines (DMAEs)…
Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space
Michael Rogenmoser, Yvan Tortorella, Davide Rossi +2
Space Cyber-Physical Systems (S-CPS) such as spacecraft and satellites strongly rely on the reliability of onboard computers to guarantee the success of their missions. Relying sol…
On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster
Michael Rogenmoser, Nils Wistoff, Pirmin Vogel +2
With the shrinking of technology nodes and the use of parallel processor clusters in hostile and critical environments, such as space, run-time faults caused by radiation are a ser…