2 papers
cs.AR2026
CovR: Coverage-Aware Hardware Verification via Reasoning-Guided Reinforcement Learning
Manar Abdelatty, Maryam Nouh, Sherief Reda
Design verification remains one of the most resource-intensive stages of hardware development, often consuming up to 70% of the total design effort. While recent work has explored…
cs.CL2025
Pluto: A Benchmark for Evaluating Efficiency of LLM-generated Hardware Code
Manar Abdelatty, Maryam Nouh, Jacob K. Rosenstein +1
Large Language Models (LLMs) are increasingly used to automate hardware design tasks, including the generation of Verilog code. While early benchmarks focus primarily on functional…