3 citations · 3 across the 4 of their papers we have counts for
5 papers
CovR: Coverage-Aware Hardware Verification via Reasoning-Guided Reinforcement Learning
Manar Abdelatty, Maryam Nouh, Sherief Reda
Design verification remains one of the most resource-intensive stages of hardware development, often consuming up to 70% of the total design effort. While recent work has explored…
Pluto: A Benchmark for Evaluating Efficiency of LLM-generated Hardware Code
Manar Abdelatty, Maryam Nouh, Jacob K. Rosenstein +1
Large Language Models (LLMs) are increasingly used to automate hardware design tasks, including the generation of Verilog code. While early benchmarks focus primarily on functional…
MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs
Manar Abdelatty, Jingxiao Ma, Sherief Reda
Large Language Models (LLMs) have been applied to various hardware design tasks, including Verilog code generation, EDA tool scripting, and RTL bug fixing. Despite this extensive e…
ChipXplore: Natural Language Exploration of Hardware Designs and Libraries
Manar Abdelatty, Jacob Rosenstein, Sherief Reda
Hardware design workflows rely on Process Design Kits (PDKs) from different fabrication nodes, each containing standard cell libraries optimized for speed, power, or density. Engin…
Microscale 3-D Capacitance Tomography with a CMOS Sensor Array
Manar Abdelatty, Joseph Incandela, Kangping Hu +3
Electrical capacitance tomography (ECT) is a nonoptical imaging technique in which a map of the interior permittivity of a volume is estimated by making capacitance measurements at…