33 citations · 50 across the 12 of their papers we have counts for
12 papers
μ-ORCA: Optimizing Acceleration for Microsecond-Scale Deep Neural Network Inference on ACAP
Shixin Ji, Jinming Zhuang, Zhuoping Yang +3
Heterogeneous reconfigurable platforms with tensor cores, such as AMD ACAP, are increasingly adopted for deep neural network (DNN) inference due to their high throughput and flexib…
DORA: Dataflow-Instruction Orchestration Architecture for DNN Acceleration
Xingzhen Chen, Zhuoping Yang, Jinming Zhuang +5
As deep neural networks develop significantly more diverse and complex, achieving high performance and efficiency on complicated DNN models faces pressing challenges. Modern DNN wo…
FILCO: Flexible Composing Architecture with Real-Time Reconfigurability for DNN Acceleration
Xingzhen Chen, Jinming Zhuang, Zhuoping Yang +5
With the development of deep neural network (DNN) enabled applications, achieving high hardware resource efficiency on diverse workloads is non-trivial in heterogeneous computing p…
PHAROS: Pipelined Heterogeneous Accelerators for Real-time Safety-critical Systems With Deadline Compliance
Shixin Ji, Jinming Zhuang, Sarah Schultz +6
Spatially partitioned heterogeneous accelerators (HAs) are increasingly adopted in embedded systems for their performance and flexibility. Yet most existing HA design frameworks op…
From Loop Nests to Silicon: Mapping AI Workloads onto AMD NPUs with MLIR-AIR
Erwei Wang, Samuel Bayliss, Andra Bisca +19
General-purpose compilers abstract away parallelism, locality, and synchronization, limiting their effectiveness on modern spatial architectures. As modern computing architectures…
AGILE: Lightweight and Efficient Asynchronous GPU-SSD Integration
Zhuoping Yang, Jinming Zhuang, Xingzhen Chen +2
GPUs are critical for compute-intensive applications, yet emerging workloads such as recommender systems, graph analytics, and data analytics often exceed GPU memory capacity. Exis…
SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration
Jinming Zhuang, Zhuoping Yang, Shixin Ji +5
With the increase in the computation intensity of the chip, the mismatch between computation layer shapes and the available computation resource significantly limits the utilizatio…
REFRESH FPGAs: Sustainable FPGA Chiplet Architectures
Peipei Zhou, Jinming Zhuang, Stephen Cahoon +6
There is a growing call for greater amounts of increasingly agile computational power for edge and cloud infrastructure to serve the computationally complex needs of ubiquitous com…
Challenges and Opportunities to Enable Large-Scale Computing via Heterogeneous Chiplets
Zhuoping Yang, Shixin Ji, Xingzhen Chen +4
Fast-evolving artificial intelligence (AI) algorithms such as large language models have been driving the ever-increasing computing demands in today's data centers. Heterogeneous c…
AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP
Zhuoping Yang, Jinming Zhuang, Jiaqi Yin +3
Arbitrary-precision integer multiplication is the core kernel of many applications in simulation, cryptography, etc. Existing acceleration of arbitrary-precision integer multiplica…
AutoMM: Energy-Efficient Multi-Data-Type Matrix Multiply Design on Heterogeneous Programmable System-on-Chip
Jinming Zhuang, Zhuoping Yang, Peipei Zhou
As the increasing complexity of Neural Network(NN) models leads to high demands for computation, AMD introduces a heterogeneous programmable system-on-chip (SoC), i.e., Versal ACAP…
CHARM: Composing Heterogeneous Accelerators for Matrix Multiply on Versal ACAP Architecture
Jinming Zhuang, Jason Lau, Hanchen Ye +10
Dense matrix multiply (MM) serves as one of the most heavily used kernels in deep learning applications. To cope with the high computation demands of these applications, heterogene…