19 citations · 37 across the 11 of their papers we have counts for
4 papers · 1 filter
LATCH: LLM-Assisted Timing Closure Harness for Post-Route FPGA Optimisation
Shu Gu, Matthew Youngman, Yuqin Zhao +5
Post-route FPGA timing closure remains expert-dependent and computationally expensive. We present LATCH (LLM-Assisted Timing Closure Harness), a two-layer framework that separates…
Closing the Loop on LLM-Generated RTL Assertions with Quality-Aware Formal Verification
Ramesh Krishnamurthy, Danial Chitnis, Themis Prodromakis
Large language model (LLM) based assertion generation is making formal verification more accessible for Register Transfer Level (RTL) designs, but three practical issues remain. Ge…
Policy-Governed LLM Routing with Intent Matching for Instrument Laboratories
Emmanuel A. Olowe, Danial Chitnis
AI tutoring systems in engineering labs face a tension between providing sufficient assistance and preserving learning opportunities. Existing systems typically offer instructors l…
EEspice: A Modular Circuit Simulation Platform with Parallel Device Model Evaluation via Graph Coloring
Xuanhao Bao, Danial Chitnis
As modern analogue/mixed-signal design increasingly relies on optimization-in-the-loop flows, such as AI and LLM-based sizing agents that repeatedly invoke SPICE-efficient, accurat…