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cs.AR2026
Closing the Loop on LLM-Generated RTL Assertions with Quality-Aware Formal Verification
Ramesh Krishnamurthy, Danial Chitnis, Themis Prodromakis
Large language model (LLM) based assertion generation is making formal verification more accessible for Register Transfer Level (RTL) designs, but three practical issues remain. Ge…
cs.AR2026
EEspice: A Modular Circuit Simulation Platform with Parallel Device Model Evaluation via Graph Coloring
Xuanhao Bao, Danial Chitnis
As modern analogue/mixed-signal design increasingly relies on optimization-in-the-loop flows, such as AI and LLM-based sizing agents that repeatedly invoke SPICE-efficient, accurat…