1 citations · 4 across the 13 of their papers we have counts for
7 papers · 1 filter
RTLGuard: A Lightweight Teacher-Student Defense for Poisoned RTL Code Generation Models
Mahshid Rezakhani, Kimia Azar, Hadi Kamali
The rapid advancement of large language models (LLMs) is driving a shift toward automated register transfer level (RTL) code generation, enabling designers to translate high-level…
SafeTune: Mitigating Data Poisoning in LLM Fine-Tuning for RTL Code Generation
Mahshid Rezakhani, Nowfel Mashnoor, Kimia Azar +1
As large language models (LLMs) are increasingly fine-tuned for hardware tasks like RTL code generation, the scarcity of high-quality datasets often leads to the use of rapidly ass…
From Language to Logic: Bridging LLMs & Formal Representations for RTL Assertion Generation
Nowfel Mashnoor, Hadi Kamali, Kimia Azar
SystemVerilog Assertions (SVA) are essential for formal verification of digital hardware, yet their manual creation demands significant expertise in both the design under verificat…
Secure eFPGA-Enabled Edge LLM Inference: Architectural and Hardware Countermeasures
Voktho Das, M Zafir Sadik Khan, Jafar Vafaei +2
Edge deployment of transformer-based models increasingly relies on ASIC accelerators due to their high performance and energy efficiency, achieved through optimized dataflows, spec…
CircuitGuard: Mitigating LLM Memorization in RTL Code Generation Against IP Leakage
Nowfel Mashnoor, Mohammad Akyash, Hadi Kamali +1
Large Language Models (LLMs) have achieved remarkable success in generative tasks, including register-transfer level (RTL) hardware synthesis. However, their tendency to memorize t…
TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization
Nowfel Mashnoor, Mohammad Akyash, Hadi Kamali +1
Achieving timing closure and design-specific optimizations in FPGA-targeted High-Level Synthesis (HLS) remains a significant challenge due to the complex interaction between archit…