1 citations · 4 across the 15 of their papers we have counts for
16 papers
RTLGuard: A Lightweight Teacher-Student Defense for Poisoned RTL Code Generation Models
Mahshid Rezakhani, Kimia Azar, Hadi Kamali
The rapid advancement of large language models (LLMs) is driving a shift toward automated register transfer level (RTL) code generation, enabling designers to translate high-level…
CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs
Mohammad Akyash, Nowfel Mashnoor, Kimia Azar +1
Recent advances in large language models (LLMs) have enabled the automatic synthesis (generation) of register-transfer level (RTL) code from natural language instructions, offering…
SafeTune: Mitigating Data Poisoning in LLM Fine-Tuning for RTL Code Generation
Mahshid Rezakhani, Nowfel Mashnoor, Kimia Azar +1
As large language models (LLMs) are increasingly fine-tuned for hardware tasks like RTL code generation, the scarcity of high-quality datasets often leads to the use of rapidly ass…
From Language to Logic: Bridging LLMs & Formal Representations for RTL Assertion Generation
Nowfel Mashnoor, Hadi Kamali, Kimia Azar
SystemVerilog Assertions (SVA) are essential for formal verification of digital hardware, yet their manual creation demands significant expertise in both the design under verificat…
Secure eFPGA-Enabled Edge LLM Inference: Architectural and Hardware Countermeasures
Voktho Das, M Zafir Sadik Khan, Jafar Vafaei +2
Edge deployment of transformer-based models increasingly relies on ASIC accelerators due to their high performance and energy efficiency, achieved through optimized dataflows, spec…
MeltRTL: Multi-Expert LLMs with Inference-time Intervention for RTL Code Generation
Nowfel Mashnoor, Mohammad Akyash, Hadi Kamali +1
The automated generation of hardware register-transfer level (RTL) code with large language models (LLMs) shows promise, yet current solutions struggle to produce syntactically and…
Bench4HLS: End-to-End Evaluation of LLMs in High-Level Synthesis Code Generation
M Zafir Sadik Khan, Kimia Azar, Hadi Kamali
In last two years, large language models (LLMs) have shown strong capabilities in code generation, including hardware design at register-transfer level (RTL). While their use in hi…
NuRedact: Non-Uniform eFPGA Architecture for Low-Overhead and Secure IP Redaction
Voktho Das, Kimia Azar, Hadi Kamali
While logic locking has been extensively studied as a countermeasure against integrated circuit (IC) supply chain threats, recent research has shifted toward reconfigurable-based r…
CircuitGuard: Mitigating LLM Memorization in RTL Code Generation Against IP Leakage
Nowfel Mashnoor, Mohammad Akyash, Hadi Kamali +1
Large Language Models (LLMs) have achieved remarkable success in generative tasks, including register-transfer level (RTL) hardware synthesis. However, their tendency to memorize t…
SAGE-HLS: Syntax-Aware AST-Guided LLM for High-Level Synthesis Code Generation
M Zafir Sadik Khan, Nowfel Mashnoor, Mohammad Akyash +2
In today's rapidly evolving field of electronic design automation (EDA), the complexity of hardware designs is increasing, necessitating more sophisticated automation solutions. Hi…
TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization
Nowfel Mashnoor, Mohammad Akyash, Hadi Kamali +1
Achieving timing closure and design-specific optimizations in FPGA-targeted High-Level Synthesis (HLS) remains a significant challenge due to the complex interaction between archit…
DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMs
Mohammad Akyash, Kimia Azar, Hadi Kamali
As one of their many applications, large language models (LLMs) have recently shown promise in automating register transfer level (RTL) code generation. However, conventional LLM d…
RTL++: Graph-enhanced LLM for RTL Code Generation
Mohammad Akyash, Kimia Azar, Hadi Kamali
As hardware design complexity escalates, there is an urgent need for advanced automation in electronic design automation (EDA). Traditional register transfer level (RTL) design met…
LLM-IFT: LLM-Powered Information Flow Tracking for Secure Hardware
Nowfel Mashnoor, Mohammad Akyash, Hadi Kamali +1
As modern hardware designs grow in complexity and size, ensuring security across the confidentiality, integrity, and availability (CIA) triad becomes increasingly challenging. Info…
Self-HWDebug: Automation of LLM Self-Instructing for Hardware Security Verification
Mohammad Akyash, Hadi Mardani Kamali
The rise of instruction-tuned Large Language Models (LLMs) marks a significant advancement in artificial intelligence (AI) (tailored to respond to specific prompts). Despite their…
Evolutionary Large Language Models for Hardware Security: A Comparative Survey
Mohammad Akyash, Hadi Mardani Kamali
Automating hardware (HW) security vulnerability detection and mitigation during the design phase is imperative for two reasons: (i) It must be before chip fabrication, as post-fabr…