1 citations · 1 across the 3 of their papers we have counts for
3 papers
cs.AR2025★ 1 cited
AssertFix: Empowering Automated Assertion Fix via Large Language Models
Hongqin Lyu, Yunlin Du, Yonghao Wang +3
Assertion-based verification (ABV) is critical in ensuring that register-transfer level (RTL) designs conform to their functional specifications. SystemVerilog Assertions (SVA) eff…
cs.AR2025
DeepAssert: An LLM-Aided Verification Framework with Fine-Grained Assertion Generation for Modules with Extracted Module Specifications
Yonghao Wang, Jiaxin Zhou, Hongqin Lyu +3
Assertion-Based Verification (ABV) is a crucial method for ensuring that logic designs conform to their architectural specifications. However, existing assertion generation methods…
cs.AR2025
Extend IVerilog to Support Batch RTL Fault Simulation
Jiaping Tang, Jianan Mu, Zizhen Liu +3
The advancement of functional safety has made RTL-level fault simulation increasingly important to achieve iterative efficiency in the early stages of design and to ensure complian…