6 citations · 10 across the 8 of their papers we have counts for
8 papers
Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures
Cyrille Chavet, Philippe Coussy, Eric Martin +1
For high throughput applications, turbo-like iterative decoders are implemented with parallel architectures. However, to be efficient parallel architectures require to avoid collis…
Synchronization Processor Synthesis for Latency Insensitive Systems
Pierre Bomel, Eric Martin, Emmanuel Boutillon
In this paper we present our contribution in terms of synchronization processor for a SoC design methodology based on the theory of the latency insensitive systems (LIS) of Carloni…
Application of a design space exploration tool to enhance interleaver generation
Cyrille Chavet, Philippe Coussy, Pascal Urard +1
This paper presents a methodology to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall performance o…
A Design Methodology for Space-Time Adapter
Cyrille Chavet, Philippe Coussy, Pascal Urard +1
This paper presents a solution to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall architecture of…
A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver
Cyrille Chavet, Philippe Coussy, Pascal Urard +1
This paper presents a solution to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall architecture of…
Memory Aware High-Level Synthesis for Embedded Systems
Gwenolé Corre, Eric Senn, Nathalie Julien +1
We introduce a new approach to take into account the memory architecture and the memory mapping in the High- Level Synthesis of Real-Time embedded systems. We formalize the memory…