activity
20062010
most citedStatic Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures

6 citations · 8 across the 5 of their papers we have counts for

collaborators

5 papers

cs.AR2010★ 6 cited

Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures

Cyrille Chavet, Philippe Coussy, Eric Martin +1

For high throughput applications, turbo-like iterative decoders are implemented with parallel architectures. However, to be efficient parallel architectures require to avoid collis…

cs.AR2007

Application of a design space exploration tool to enhance interleaver generation

Cyrille Chavet, Philippe Coussy, Pascal Urard +1

This paper presents a methodology to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall performance o…

cs.AR2007

A Design Methodology for Space-Time Adapter

Cyrille Chavet, Philippe Coussy, Pascal Urard +1

This paper presents a solution to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall architecture of…

cs.AR2007★ 2 cited

A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver

Cyrille Chavet, Philippe Coussy, Pascal Urard +1

This paper presents a solution to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall architecture of…

cs.AR2006

High-level synthesis under I/O Timing and Memory constraints

Philippe Coussy, Gwenolé Corre, Pierre Bomel +2

The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper…