5 papers
RTLCurator: Label-Efficient Data Curation for RTL Generation
Siyang Cai, Cangyuan Li, Wenjing Chang +4
Training large language models (LLMs) to write register-transfer level (RTL) requires large corpora of paired specifications and code, and such data is scarce enough that most publ…
When Fuzzing Meets Understanding: LLM-Driven Semantic Test Generation for RTL Verification
Kun Wang, Cangyuan Li, Kaiyan Chang +3
The growing complexity of modern chips poses significant challenges to hardware verification. In recent years, coverage-guided fuzzing has emerged as a promising approach for impro…
Wrong Code, Right Structure: Learning Netlist Representations from Imperfect LLM-Generated RTL
Siyang Cai, Cangyuan Li, Haoyu Gao +3
Learning effective netlist representations is fundamentally constrained by the scarcity of labeled datasets, as real designs are protected by Intellectual Property (IP) and costly…
RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Framework
Kun Wang, Kaiyan Chang, Mengdi Wang +4
Recent advances of large language models in the field of Verilog generation have raised several ethical and security concerns, such as code copyright protection and dissemination o…
Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation
Kaiyan Chang, Zhirong Chen, Yunhao Zhou +9
Natural language interfaces have exhibited considerable potential in the automation of Verilog generation derived from high-level specifications through the utilization of large la…