35 citations · 62 across the 8 of their papers we have counts for
8 papers
CascadeLUT: Information-Ordered Streaming Inference for Bandwidth-Constrained FPGAs
Oliver Cassidy, Marta Andronic, George A. Constantinides
Mapping neural networks to FPGAs enables low-latency, energy-efficient inference, particularly for lookup table (LUT)-based models that eliminate multipliers and map directly to re…
Training with Fewer Bits: Unlocking Edge LLMs Training with Stochastic Rounding
Taowen Liu, Marta Andronic, Deniz Gündüz +1
LLM training is resource-intensive. Quantized training improves computational and memory efficiency but introduces quantization noise, which can hinder convergence and degrade mode…
NeuraLUT-Assemble: Hardware-aware Assembling of Sub-Neural Networks for Efficient LUT Inference
Marta Andronic, George A. Constantinides
Efficient neural networks (NNs) leveraging lookup tables (LUTs) have demonstrated significant potential for emerging AI applications, particularly when deployed on field-programmab…
PolyLUT: Ultra-low Latency Polynomial Inference with Hardware-Aware Structured Pruning
Marta Andronic, Jiawen Li, George A. Constantinides
Standard deep neural network inference involves the computation of interleaved linear maps and nonlinear activation functions. Prior work for ultra-low latency implementations has…
ReducedLUT: Table Decomposition with "Don't Care" Conditions
Oliver Cassidy, Marta Andronic, Samuel Coward +1
Lookup tables (LUTs) are frequently used to efficiently store arrays of precomputed values for complex mathematical computations. When used in the context of neural networks, these…
BitMoD: Bit-serial Mixture-of-Datatype LLM Acceleration
Yuzong Chen, Ahmed F. AbouElhamayed, Xilai Dai +4
Large language models (LLMs) have demonstrated remarkable performance across various machine learning tasks. Yet the substantial memory footprint of LLMs significantly hinders thei…
NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions
Marta Andronic, George A. Constantinides
Field-Programmable Gate Array (FPGA) accelerators have proven successful in handling latency- and resource-critical deep neural network (DNN) inference tasks. Among the most comput…
PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference
Marta Andronic, George A. Constantinides
Field-programmable gate arrays (FPGAs) are widely used to implement deep learning inference. Standard deep neural network inference involves the computation of interleaved linear m…