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cs.CV2026
SCALE: Self-Supervised Constraint-Aware Layout GEneration for Local P&R DRV Fixing at Advanced Nodes
Chia-Tung Ho, Haoyu Yang, Guanglei Zhou +6
As semiconductor manufacturing advances toward sub-2nm nodes, local place-and-route (P&R) design-rule violation (DRV) fixing is increasingly limited by complex rule interactions, d…
cs.CV2024
PatternPaint: Practical Layout Pattern Generation Using Diffusion-Based Inpainting
Guanglei Zhou, Bhargav Korrapati, Gaurav Rajavendra Reddy +5
Generating diverse VLSI layout patterns is essential for various downstream tasks in design for manufacturing, as design rules continually evolve during the development of new tech…