19 citations · 43 across the 10 of their papers we have counts for
10 papers
Efficient Implementation of RISC-V Vector Permutation Instructions
Vasileios Titopoulos, George Alexakis, Chrysostomos Nicopoulos +1
RISC-V CPUs leverage the RVV (RISC-V Vector) extension to accelerate data-parallel workloads. In addition to arithmetic operations, RVV includes powerful permutation instructions t…
Periodic Online Testing for Sparse Systolic Tensor Arrays
Christodoulos Peltekis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
Modern Machine Learning (ML) applications often benefit from structured sparsity, a technique that efficiently reduces model complexity and simplifies handling of sparse data in ha…
Register Dispersion: Reducing the Footprint of the Vector Register File in Vector Engines of Low-Cost RISC-V CPUs
Vasileios Titopoulos, George Alexakis, Kosmas Alexandridis +2
The deployment of Machine Learning (ML) applications at the edge on resource-constrained devices has accentuated the need for efficient ML processing on low-cost processors. While…
Optimizing Structured-Sparse Matrix Multiplication in RISC-V Vector Processors
Vasileios Titopoulos, Kosmas Alexandridis, Christodoulos Peltekis +2
Structured sparsity has been proposed as an efficient way to prune the complexity of Machine Learning (ML) applications and to simplify the handling of sparse data in hardware. Acc…
DeMM: A Decoupled Matrix Multiplication Engine Supporting Relaxed Structured Sparsity
Christodoulos Peltekis, Vasileios Titopoulos, Chrysostomos Nicopoulos +1
Deep Learning (DL) has achieved unprecedented success in various application domains. Meanwhile, model pruning has emerged as a viable solution to reduce the footprint of DL models…
IndexMAC: A Custom RISC-V Vector Instruction to Accelerate Structured-Sparse Matrix Multiplications
V. Titopoulos, K. Alexandridis, C. Peltekis +2
Structured sparsity has been proposed as an efficient way to prune the complexity of modern Machine Learning (ML) applications and to simplify the handling of sparse data in hardwa…
The Case for Asymmetric Systolic Array Floorplanning
C. Peltekis, D. Filippas, G. Dimitrakopoulos +1
The widespread proliferation of deep learning applications has triggered the need to accelerate them directly in hardware. General Matrix Multiplication (GEMM) kernels are elementa…
Low-Power Data Streaming in Systolic Arrays with Bus-Invert Coding and Zero-Value Clock Gating
C. Peltekis, D. Filippas, G. Dimitrakopoulos +1
Systolic Array (SA) architectures are well suited for accelerating matrix multiplications through the use of a pipelined array of Processing Elements (PEs) communicating with local…
Reduced-Precision Floating-Point Arithmetic in Systolic Arrays with Skewed Pipelines
D. Filippas, C. Peltekis, G. Dimitrakopoulos +1
The acceleration of deep-learning kernels in hardware relies on matrix multiplications that are executed efficiently on Systolic Arrays (SA). To effectively trade off deep-learning…
ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining
C. Peltekis, D. Filippas, G. Dimitrakopoulos +2
Convolutional Neural Networks (CNNs) are the state-of-the-art solution for many deep learning applications. For maximum scalability, their computation should combine high performan…