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20242026
most citedCB-SpMV:A Data Aggregating and Balance Algorithm for Cache-Friendly Block-Based SpMV on GPUs

2 citations · 3 across the 14 of their papers we have counts for

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6 papers · 1 filter

cs.DC2026

DB-SpMSpV: Dual-View Blocked Sparse Matrix-Sparse Vector Multiplication for Dynamic GPU Workloads

Xing Cong, Chenhao Xie, Rui Wang +3

Sparse Matrix-Sparse Vector Multiplication (SpMSpV) is a core primitive in graph traversal, sparse linear algebra, and sparse model inference. Its input vector is often dynamically…

cs.SE2026

Can LLMs Really Recover Microservice Failures? A Recovery-Aware Evaluation of Diagnosis-to-Action Reasoning

Jiaxing Qi, Zhongzhi Luan, Hongyu Zhang +5

Large language models (LLMs) are increasingly used to interpret operational evidence and assist incident response in cloud-native microservice systems. However, recovery-oriented u…

cs.DC2026

RATrain: A Resource-Aware Training Runtime for Large Language Models on Bandwidth-Constrained Heterogeneous Supercomputing Platforms

Yao Lu, Shiqing Ma, Zhongzhi Luan +5

Production heterogeneous supercomputing platforms are increasingly used to host large language model (LLM) training workloads. However, existing GPU-oriented training runtimes typi…

cs.DC2026

Bandwidth-Aware LLM Inference on Heterogeneous Many-Core Supercomputers

Yao Lu, Zhongzhi Luan, Gen Li +6

Large language model (LLM) inference is limited by high computational cost and memory bandwidth demands, making deployment on heterogeneous many-core processors challenging. Taking…

cs.DC2026★ 2 cited

CB-SpMV:A Data Aggregating and Balance Algorithm for Cache-Friendly Block-Based SpMV on GPUs

Xing Cong, Fukai Sun, Yifan Chen +3

Sparse matrix-vector multiplication (SpMV) is crucial in computational science, engineering, and machine learning. Despite substantial efforts to improve SpMV performance on GPUs t…

cs.AR2026

AccelSync: Verifying Synchronization Coverage in Accelerator Pipeline Programs

Hangcheng An, Rui Wang, Depei Qian

AI accelerator operators are compiled into multi-stage pipeline programs where DMA, vector, matrix, and scalar units execute concurrently on shared on-chip buffers. A missing or mi…