4 papers
Unveiling the Scaling Potential of Drain Merge through Active (DMtA) in CFETs: Breaking the Super-Via Bottlenecks and Unlocking New PPA Boosters
Jingru Jiang, Haoran Lu, Kairong Guo +11
Drain merge (DM), a super via vertically connecting the common S/D terminals of stacked n/pFETs in Complementary FETs (CFETs), blocks further parasitic optimization and cell scalin…
Overlay-aware Variation Study of Flip FET and Benchmark with CFET
Wanyue Peng, Haoran Lu, Jingru Jiang +5
In this work, we carried out an overlay-aware variation study on Flip FET (FFET) considering the impact on RC parasitics induced by the lithography misalignment in backside process…
A Tale of Two Sides of Wafer: Physical Implementation and Block-Level PPA on Flip FET with Dual-sided Signals
Haoran Lu, Xun Jiang, Yanbang Chu +7
As the conventional scaling of logic devices comes to an end, functional wafer backside and 3D transistor stacking are consensus for next-generation logic technology, offering cons…
From Flip FET to Flip 3D Integration (F3D): Maximizing the Scaling Potential of Wafer Both Sides Beyond Conventional 3D Integration
Heng Wu, Haoran Lu, Wanyue Peng +13
In this work, we proposed a new 3D integration technology: the Flip 3D integration (F3D), consisting of the 3D transistor stacking, the 3D dual-sided interconnects, the 3D die-to-d…