activity
20242026
most citedTrIM, Triangular Input Movement Systolic Array for Convolutional Neural Networks: Architecture and Hardware Implementation

4 citations · 6 across the 11 of their papers we have counts for

collaborators

13 papers

cs.AI2026

LATCH: LLM-Assisted Timing Closure Harness for Post-Route FPGA Optimisation

Shu Gu, Matthew Youngman, Yuqin Zhao +5

Post-route FPGA timing closure remains expert-dependent and computationally expensive. We present LATCH (LLM-Assisted Timing Closure Harness), a two-layer framework that separates…

cs.AI2026

AgenticSizing: A Large Language Model-based Multi-Agent Framework for Analog Circuit Sizing

Yijia Hao, Pratibha Verma, Dongxu Guo +4

Analog circuit sizing remains a challenging and time-consuming task due to the large design space, strong performance trade-offs, and increasing circuit complexity in scaled techno…

cs.AR2026

Gen-TAS: A Generative AI-Aided Hardware-Software Task Allocation Framework for FPGA-GPP Heterogeneous Systems

Mary Kong, Yuqin Zhao, Semih Vazgecen +2

FPGA-GPP heterogeneous systems combine software flexibility with the performance and energy efficiency of reconfigurable hardware. However, determining which application tasks shou…

cs.CV2026

Vision-centric generative AI models: A software-hardware perspective

Eleni Tselepi, Cristian Sestito, Shady Agwa +1

Vision generative artificial intelligence (AI) has emerged as one of the most rapidly advancing areas of deep learning. The explosion of multimodal models has made them widely asso…

cs.AR2026

LLMs in Digital EDA: A perspective on shifting roles from Generation to Orchestration

Matthew Youngman, Cristian Sestito, Themis Prodromakis

Electronic design automation (EDA) has advanced engineering productivity through successive generations of tooling that progressively automate synthesis, optimisation, and verifica…

cs.CV2026

Non-frontal face recognition using GANs and memristor-based classifiers

Semih Vazgecen, Cristian Sestito, Spyros Stathopoulos +1

Face recognition systems have advanced significantly through deep learning techniques, delivering high performance and robustness in complex scenarios. However, these approaches in…

cs.AR2026

D-Legion: A Scalable Many-Core Architecture for Accelerating Matrix Multiplication in Quantized LLMs

Ahmed J. Abdelmaksoud, Cristian Sestito, Shiwei Wang +1

The performance gains obtained by large language models (LLMs) are closely linked to their substantial computational and memory requirements. Quantized LLMs offer significant advan…

eess.SY2026

A flexible language model-assisted electronic design automation framework

Cristian Sestito, Panagiota Kontou, Pratibha Verma +5

Large language models (LLMs) are transforming electronic design automation (EDA) by enhancing design stages such as schematic design, simulation, netlist synthesis, and place-and-r…

cs.AR2025

ADiP: Adaptive-Precision Systolic Array for Matrix Multiplication Acceleration

Ahmed J. Abdelmaksoud, Cristian Sestito, Shiwei Wang +1

Transformers are at the core of modern AI nowadays. They rely heavily on matrix multiplication and require efficient acceleration due to their substantial memory and computational…

cs.AR2025

3D-TrIM: A Memory-Efficient Spatial Computing Architecture for Convolution Workloads

Cristian Sestito, Ahmed J. Abdelmaksoud, Shady Agwa +1

The Von Neumann bottleneck, which relates to the energy cost of moving data from memory to on-chip core and vice versa, is a serious challenge in state-of-the-art AI architectures,…

eess.SP2025★ 1 cited

L-Sort: On-chip Spike Sorting with Efficient Median-of-Median Detection and Localization-based Clustering

Yuntao Han, Yihan Pan, Xiongfei Jiang +4

Spike sorting is a critical process for decoding large-scale neural activity from extracellular recordings. The advancement of neural probes facilitates the recording of a high num…

cs.AR2024★ 4 cited

TrIM, Triangular Input Movement Systolic Array for Convolutional Neural Networks: Architecture and Hardware Implementation

Cristian Sestito, Shady Agwa, Themis Prodromakis

Modern hardware architectures for Convolutional Neural Networks (CNNs), other than targeting high performance, aim at dissipating limited energy. Reducing the data movement cost be…

cs.AI2024★ 1 cited

TrIM, Triangular Input Movement Systolic Array for Convolutional Neural Networks: Dataflow and Analytical Modelling

Cristian Sestito, Shady Agwa, Themis Prodromakis

In order to follow the ever-growing computational complexity and data intensity of state-of-the-art AI models, new computing paradigms are being proposed. These paradigms aim at ac…