activity
20232026
most citedSoC-Tuner: An Importance-guided Exploration Framework for DNN-targeting SoC Design

4 citations · 5 across the 6 of their papers we have counts for

collaborators

6 papers

cs.AR2026

LongRTL: Graph-Similarity-Guided LLM-driven Long Context RTL Optimization

Yuyang Ye, Che-Kuan Shen, Xiangfei Hu +5

Large Language Models (LLMs) show great promise in RTL code generation and optimization. However, real-world RTL designs are typically long, entangled, and poorly modularized, posi…

cs.AR2026

CPPL: A Circuit Prompt Programming Language

Shuo Yin, Yihe Wang, Lancheng Zou +6

Large language models (LLMs) have shown promise in register-transfer level (RTL) design automation, but direct RTL generation remains difficult to validate, optimize, and integrate…

cs.AR2026★ 1 cited

PipeRTL: Timing-Aware Pipeline Optimization at IR-Level for RTL Generation

Shuo Yin, Fangzhou Liu, Lancheng Zou +6

Modern hardware compilers increasingly rely on rich intermediate representations (IRs) to preserve optimization-relevant semantics before generating RTL code. However, one importan…

cs.LG2025

PermLLM: Learnable Channel Permutation for N:M Sparse Large Language Models

Lancheng Zou, Shuo Yin, Zehua Pei +3

Channel permutation is a powerful technique for enhancing the accuracy of N:M sparse models by reordering the channels of weight matrices to prioritize the retention of important w…

cs.LG2025

TorchResist: Open-Source Differentiable Resist Simulator

Zixiao Wang, Jieya Zhou, Su Zheng +5

Recent decades have witnessed remarkable advancements in artificial intelligence (AI), including large language models (LLMs), image and video generative models, and embodied AI sy…

cs.AR2023★ 4 cited

SoC-Tuner: An Importance-guided Exploration Framework for DNN-targeting SoC Design

Shixin Chen, Su Zheng, Chen Bai +4

Designing a system-on-chip (SoC) for deep neural network (DNN) acceleration requires balancing multiple metrics such as latency, power, and area. However, most existing methods ign…