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Dimitrios Tsaras

3 papers hereh-index 364 citations8 works total

Matching runs newest-first, so older work may not be attached to this profile yet.

author position
  • first author1
  • middle author2

Across the 3 of 3 papers where every author was matched, so the position is known.

fields
  • cs.LG2
  • cs.AR1

identity via Semantic Scholar / OpenAlex

activity
20242026
collaborators

3 papers

cs.AR2026

RTLScout: Joint Agentic Code and Synthesis Optimization for Efficient Digital Circuits

Felix Arnold, Ryan Amaudruz, Dimitrios Tsaras +2

We present RTLScout, an autonomous system that combines LLM-driven agentic design with circuit-level synthesis optimization and arithmetic architecture sweeps. An LLM agent iterati…

cs.LG2025

The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimation

Reza Moravej, Saurabh Bodhe, Zhanguang Zhang +6

Logic synthesis is a crucial phase in the circuit design process, responsible for transforming hardware description language (HDL) designs into optimized netlists. However, traditi…

cs.LG2024

ShortCircuit: AlphaZero-Driven Circuit Design

Dimitrios Tsaras, Antoine Grosnit, Lei Chen +3

Chip design relies heavily on generating Boolean circuits, such as AND-Inverter Graphs (AIGs), from functional descriptions like truth tables. This generation operation is a key pr…

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