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cs.AR2026
DAE4HLS: Exposing Memory-Level Parallelism for High-Level Synthesis using Explicit Decoupling
David Metz, Magnus Själander
High-level synthesis (HLS) performs well for simple memory access patterns, such as for sequential accesses that can be turned into bursts, or for memory accesses into small datase…
cs.AR2025★ 1 cited
Optimizing Energy Efficiency in Subthreshold RISC-V Cores
Asbjørn Djupdal, Magnus Själander, Magnus Jahre +2
Our goal in this paper is to understand how to maximize energy efficiency when designing standard-ISA processor cores for subthreshold operation. We hence develop a custom subthres…