3 papers
cs.AR2025
Dynamic Tsetlin Machine Accelerators for On-Chip Training at the Edge using FPGAs
Gang Mao, Tousif Rahman, Sidharth Maheshwari +4
The increased demand for data privacy and security in machine learning (ML) applications has put impetus on effective edge training on Internet-of-Things (IoT) nodes. Edge training…
cs.AR2025
Runtime Tunable Tsetlin Machines for Edge Inference on eFPGAs
Tousif Rahman, Gang Mao, Bob Pattison +5
Embedded Field-Programmable Gate Arrays (eFPGAs) allow for the design of hardware accelerators of edge Machine Learning (ML) applications at a lower power budget compared with trad…
cs.AR2024★ 1 cited
MATADOR: Automated System-on-Chip Tsetlin Machine Design Generation for Edge Applications
Tousif Rahman, Gang Mao, Sidharth Maheshwari +2
System-on-Chip Field-Programmable Gate Arrays (SoC-FPGAs) offer significant throughput gains for machine learning (ML) edge inference applications via the design of co-processor ac…