3 papers
cs.AR2026
Closing the Loop on LLM-Generated RTL Assertions with Quality-Aware Formal Verification
Ramesh Krishnamurthy, Danial Chitnis, Themis Prodromakis
Large language model (LLM) based assertion generation is making formal verification more accessible for Register Transfer Level (RTL) designs, but three practical issues remain. Ge…
cs.AR2026
DISCA: A Digital In-memory Stochastic Computing Architecture Using A Compressed Bent-Pyramid Format
Shady Agwa, Yikang Shen, Shiwei Wang +1
Nowadays, we are witnessing an Artificial Intelligence revolution that dominates the technology landscape in various application domains, such as healthcare, robotics, automotive,…
cs.AR2026
ADiP: Adaptive-Precision Systolic Array for Matrix Multiplication Acceleration
Ahmed J. Abdelmaksoud, Cristian Sestito, Shiwei Wang +1
Transformers are at the core of modern AI nowadays. They rely heavily on matrix multiplication and require efficient acceleration due to their substantial memory and computational…