8 papers
Closing the Loop on LLM-Generated RTL Assertions with Quality-Aware Formal Verification
Ramesh Krishnamurthy, Danial Chitnis, Themis Prodromakis
Large language model (LLM) based assertion generation is making formal verification more accessible for Register Transfer Level (RTL) designs, but three practical issues remain. Ge…
Policy-Governed LLM Routing with Intent Matching for Instrument Laboratories
Emmanuel A. Olowe, Danial Chitnis
AI tutoring systems in engineering labs face a tension between providing sufficient assistance and preserving learning opportunities. Existing systems typically offer instructors l…
EEspice: A Modular Circuit Simulation Platform with Parallel Device Model Evaluation via Graph Coloring
Xuanhao Bao, Danial Chitnis
As modern analogue/mixed-signal design increasingly relies on optimization-in-the-loop flows, such as AI and LLM-based sizing agents that repeatedly invoke SPICE-efficient, accurat…
EEsizer: LLM-Based AI Agent for Sizing of Analog and Mixed Signal Circuit
Chang Liu, Danial Chitnis
The design of Analog and Mixed-Signal (AMS) integrated circuits (ICs) often involves significant manual effort, especially during the transistor sizing process. While Machine Learn…
EEschematic: Multimodal-LLM Based AI Agent for Schematic Generation of Analog Circuit
Chang Liu, Danial Chitnis
Circuit schematics play a crucial role in analog integrated circuit design, serving as the primary medium for human understanding and verification of circuit functionality. While r…
LLM-based AI Agent for Sizing of Analog and Mixed Signal Circuit
Chang Liu, Emmanuel A. Olowe, Danial Chitnis
The design of Analog and Mixed-Signal (AMS) integrated circuits (ICs) often involves significant manual effort, especially during the transistor sizing process. While Machine Learn…