2 papers
cs.CR2026
AutoTrans: AI-Assisted Automatic Translation of Security Assertions for RISC-V Processors
Sharjeel Imtiaz, Uljana Reinsalu, Tara Ghasempouri
Reusing a set of verified security assertions across RISC-V processor targets remains one of the most expensive bottlenecks in hardware security verification. Manual translation ta…
cs.CR2025
Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study
Sharjeel Imtiaz, Uljana Reinsalu, Tara Ghasempouri
RISC-V is gaining popularity for its adaptability and cost-effectiveness in processor design. With the increasing adoption of RISC-V, the importance of implementing robust security…